From e573ddb5814ac1c9cafd6376c3052ca01dddeae8 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Fri, 17 Nov 2023 20:22:02 -0600
Subject: tb: add test: fifo

---
 rtl/gfx/gfx_fifo.sv  | 15 +++++++++-----
 rtl/top/test_fifo.sv | 20 +++++++++++++++++++
 tb/top/test_fifo.py  | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 86 insertions(+), 5 deletions(-)
 create mode 100644 rtl/top/test_fifo.sv
 create mode 100644 tb/top/test_fifo.py

diff --git a/rtl/gfx/gfx_fifo.sv b/rtl/gfx/gfx_fifo.sv
index 7314b4b..e9fa8f5 100644
--- a/rtl/gfx/gfx_fifo.sv
+++ b/rtl/gfx/gfx_fifo.sv
@@ -13,10 +13,15 @@ module gfx_fifo
 	output logic[WIDTH - 1:0] out
 );
 
-	logic full_if_eq, in_stall, out_stall, may_read, may_write, read, read_ok, write;
+	logic do_read, do_write, full_if_eq, in_stall, out_stall,
+	      may_read, may_write, read, read_ok, write;
+
 	logic[WIDTH - 1:0] fifo[DEPTH], read_data, write_data;
 	logic[$clog2(DEPTH) - 1:0] read_ptr, write_ptr;
 
+	assign do_read = read && may_read;
+	assign do_write = write && may_write;
+
 	always_comb begin
 		may_read = full_if_eq;
 		may_write = !full_if_eq;
@@ -70,15 +75,15 @@ module gfx_fifo
 			if (!out_stall)
 				read_ok <= read && may_read;
 
-			if (read && may_read)
+			if (do_read)
 				read_ptr <= read_ptr + 1;
 
-			if (write && may_write)
+			if (do_write)
 				write_ptr <= write_ptr + 1;
 
-			if (read && !write)
+			if (do_read && !do_write)
 				full_if_eq <= 0;
-			else if (!read && write)
+			else if (!do_read && do_write)
 				full_if_eq <= 1;
 		end
 
diff --git a/rtl/top/test_fifo.sv b/rtl/top/test_fifo.sv
new file mode 100644
index 0000000..2641c61
--- /dev/null
+++ b/rtl/top/test_fifo.sv
@@ -0,0 +1,20 @@
+module test_fifo
+(
+	input  logic      clk,
+	                  rst_n,
+
+	input  logic[7:0] in,
+	input  logic      in_valid,
+	output logic      in_ready,
+
+	input  logic      out_ready,
+	output logic      out_valid,
+	output logic[7:0] out
+);
+
+	gfx_fifo #(.WIDTH($bits(in)), .DEPTH(8)) dut
+	(
+		.*
+	);
+
+endmodule
diff --git a/tb/top/test_fifo.py b/tb/top/test_fifo.py
new file mode 100644
index 0000000..259d03d
--- /dev/null
+++ b/tb/top/test_fifo.py
@@ -0,0 +1,56 @@
+import itertools
+
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import ClockCycles, RisingEdge, Timer
+from cocotb_bus.drivers import BitDriver
+
+@cocotb.test()
+async def fifo(dut):
+    await cocotb.start(Clock(dut.clk, 2).start())
+
+    dut.in_valid.value = 0
+    dut.out_ready.value = 0
+
+    dut.rst_n.value = 1
+    await Timer(1)
+    dut.rst_n.value = 0
+    await Timer(1)
+    dut.rst_n.value = 1
+
+    async def send():
+        in_ = getattr(dut, 'in')
+        in_ready = dut.in_ready
+        in_valid = dut.in_valid
+
+        val = 0
+        while True:
+            in_.value = val
+            await RisingEdge(dut.clk)
+            if in_valid.value and in_ready.value:
+                val = (val + 1) & 0xff
+
+    async def recv():
+        out = dut.out
+        out_ready = dut.out_ready
+        out_valid = dut.out_valid
+
+        val = 0
+        while True:
+            await RisingEdge(dut.clk)
+            if out_valid.value and out_ready.value:
+                assert out.value == val, f'expected {val}, got {out.value.integer}'
+                val = (val + 1) & 0xff
+
+    await cocotb.start(send())
+    await cocotb.start(recv())
+
+    await ClockCycles(dut.clk, 2)
+
+    ready_driver = BitDriver(dut.out_ready, dut.clk)
+    valid_driver = BitDriver(dut.in_valid, dut.clk)
+
+    ready_driver.start((1, i % 5) for i in itertools.count())
+    valid_driver.start((1 + (i % 2), (i + 1) % 3) for i in itertools.count())
+
+    await ClockCycles(dut.clk, 1 << 16)
-- 
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