From c14209fa2a72d62e06a5480b3652fe4680978349 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 1 Nov 2022 21:50:18 -0600
Subject: Add the cp15 subsystem

---
 conspiracion.qsf            |  1 +
 rtl/core/arm810.sv          | 12 ++++++++++++
 rtl/core/control/control.sv |  5 ++++-
 rtl/core/cp15/cp15.sv       | 13 +++++++++++++
 4 files changed, 30 insertions(+), 1 deletion(-)
 create mode 100644 rtl/core/cp15/cp15.sv

diff --git a/conspiracion.qsf b/conspiracion.qsf
index 1b11931..33bcca9 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -141,6 +141,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/mux.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/stall.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/coproc.sv
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 6e4b777..71233a3 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -137,4 +137,16 @@ module arm810
 		.*
 	);
 
+	logic coproc;
+	word coproc_read, coproc_write;
+
+	core_cp15 cp15
+	(
+		.transfer(coproc),
+		.dec(dec_coproc),
+		.read(coproc_read),
+		.write(coproc_write),
+		.*
+	);
+
 endmodule
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 4169986..fe70a3c 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -50,7 +50,8 @@ module core_control
 	                       mul,
 	                       mul_add,
 	                       mul_long,
-	                       mul_signed
+	                       mul_signed,
+	                       coproc
 );
 
 	logic final_writeback, final_update_flags, ldst, ldst_pre, ldst_increment,
@@ -156,6 +157,8 @@ module core_control
 					mul_long <= dec_mul.long_mul;
 					mul_signed <= dec_mul.signed_mul;
 
+					coproc <= dec.coproc;
+
 					mem_regs <= dec_ldst.regs;
 					mem_write <= !dec_ldst.load;
 
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
new file mode 100644
index 0000000..b31ccb7
--- /dev/null
+++ b/rtl/core/cp15/cp15.sv
@@ -0,0 +1,13 @@
+`include "core/uarch.sv"
+
+module core_cp15
+(
+	input  logic         clk,
+	                     transfer,
+	input  coproc_decode dec,
+	input  word          write,
+
+	output word          read
+);
+
+endmodule
-- 
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