From bc98bc905c2e796f0d587719196f7e4bf344510a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 29 Sep 2023 19:50:01 -0600 Subject: platform: add CPUs and caches to qsys --- cache_hw.tcl | 256 +++++++++++++++++++++++++++++++ core_hw.tcl | 2 +- platform.qsys | 213 +++++++++++++++++++++++--- rtl/cache/cache.sv | 64 ++++---- rtl/cache/cache_control.sv | 373 +++++++++++++++++++++++++++++++++++++++++++++ rtl/cache/control.sv | 373 --------------------------------------------- rtl/cache/defs.sv | 8 + rtl/core/cp15/cache.sv | 15 -- rtl/core/cp15/cache_ops.sv | 15 ++ 9 files changed, 876 insertions(+), 443 deletions(-) create mode 100644 cache_hw.tcl create mode 100644 rtl/cache/cache_control.sv delete mode 100644 rtl/cache/control.sv delete mode 100644 rtl/core/cp15/cache.sv create mode 100644 rtl/core/cp15/cache_ops.sv diff --git a/cache_hw.tcl b/cache_hw.tcl new file mode 100644 index 0000000..7cae804 --- /dev/null +++ b/cache_hw.tcl @@ -0,0 +1,256 @@ +# TCL File Generated by Component Editor 20.1 +# Sat Sep 30 02:25:24 GMT 2023 +# DO NOT MODIFY + + +# +# cache "8KiB 1-way cache w/ controller" v1.0 +# 2023.09.30.02:25:24 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module cache +# +set_module_property DESCRIPTION "" +set_module_property NAME cache +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME "8KiB 1-way cache w/ controller" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL cache +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/cache/cache.sv TOP_LEVEL_FILE +add_fileset_file cache_control.sv SYSTEM_VERILOG PATH rtl/cache/cache_control.sv +add_fileset_file defs.sv SYSTEM_VERILOG PATH rtl/cache/defs.sv +add_fileset_file offsets.sv SYSTEM_VERILOG PATH rtl/cache/offsets.sv +add_fileset_file routing.sv SYSTEM_VERILOG PATH rtl/cache/routing.sv +add_fileset_file sram.sv SYSTEM_VERILOG PATH rtl/cache/sram.sv + + +# +# parameters +# +add_parameter TOKEN_AT_RESET INTEGER 0 +set_parameter_property TOKEN_AT_RESET DEFAULT_VALUE 0 +set_parameter_property TOKEN_AT_RESET DISPLAY_NAME TOKEN_AT_RESET +set_parameter_property TOKEN_AT_RESET TYPE INTEGER +set_parameter_property TOKEN_AT_RESET UNITS None +set_parameter_property TOKEN_AT_RESET ALLOWED_RANGES -2147483648:2147483647 +set_parameter_property TOKEN_AT_RESET AFFECTS_GENERATION false +set_parameter_property TOKEN_AT_RESET HDL_PARAMETER true + + +# +# display items +# + + +# +# connection point clock_sink +# +add_interface clock_sink clock end +set_interface_property clock_sink clockRate 0 +set_interface_property clock_sink ENABLED true +set_interface_property clock_sink EXPORT_OF "" +set_interface_property clock_sink PORT_NAME_MAP "" +set_interface_property clock_sink CMSIS_SVD_VARIABLES "" +set_interface_property clock_sink SVD_ADDRESS_GROUP "" + +add_interface_port clock_sink clk clk Input 1 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock_sink +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst_n reset_n Input 1 + + +# +# connection point core +# +add_interface core avalon end +set_interface_property core addressUnits WORDS +set_interface_property core associatedClock clock_sink +set_interface_property core associatedReset reset_sink +set_interface_property core bitsPerSymbol 8 +set_interface_property core burstOnBurstBoundariesOnly false +set_interface_property core burstcountUnits WORDS +set_interface_property core explicitAddressSpan 0 +set_interface_property core holdTime 0 +set_interface_property core linewrapBursts false +set_interface_property core maximumPendingReadTransactions 0 +set_interface_property core maximumPendingWriteTransactions 0 +set_interface_property core readLatency 0 +set_interface_property core readWaitTime 1 +set_interface_property core setupTime 0 +set_interface_property core timingUnits Cycles +set_interface_property core writeWaitTime 0 +set_interface_property core ENABLED true +set_interface_property core EXPORT_OF "" +set_interface_property core PORT_NAME_MAP "" +set_interface_property core CMSIS_SVD_VARIABLES "" +set_interface_property core SVD_ADDRESS_GROUP "" + +add_interface_port core core_address address Input 30 +add_interface_port core core_read read Input 1 +add_interface_port core core_write write Input 1 +add_interface_port core core_waitrequest waitrequest Output 1 +add_interface_port core core_readdata readdata Output 32 +add_interface_port core core_writedata writedata Input 32 +add_interface_port core core_byteenable byteenable Input 4 +set_interface_assignment core embeddedsw.configuration.isFlash 0 +set_interface_assignment core embeddedsw.configuration.isMemoryDevice 0 +set_interface_assignment core embeddedsw.configuration.isNonVolatileStorage 0 +set_interface_assignment core embeddedsw.configuration.isPrintableDevice 0 + + +# +# connection point out_data +# +add_interface out_data avalon_streaming start +set_interface_property out_data associatedClock clock_sink +set_interface_property out_data associatedReset reset_sink +set_interface_property out_data dataBitsPerSymbol 8 +set_interface_property out_data errorDescriptor "" +set_interface_property out_data firstSymbolInHighOrderBits true +set_interface_property out_data maxChannel 0 +set_interface_property out_data readyLatency 0 +set_interface_property out_data ENABLED true +set_interface_property out_data EXPORT_OF "" +set_interface_property out_data PORT_NAME_MAP "" +set_interface_property out_data CMSIS_SVD_VARIABLES "" +set_interface_property out_data SVD_ADDRESS_GROUP "" + +add_interface_port out_data out_data_ready ready Input 1 +add_interface_port out_data out_data_valid valid Output 1 +add_interface_port out_data out_data data Output 160 + + +# +# connection point in_data +# +add_interface in_data avalon_streaming end +set_interface_property in_data associatedClock clock_sink +set_interface_property in_data associatedReset reset_sink +set_interface_property in_data dataBitsPerSymbol 8 +set_interface_property in_data errorDescriptor "" +set_interface_property in_data firstSymbolInHighOrderBits true +set_interface_property in_data maxChannel 0 +set_interface_property in_data readyLatency 0 +set_interface_property in_data ENABLED true +set_interface_property in_data EXPORT_OF "" +set_interface_property in_data PORT_NAME_MAP "" +set_interface_property in_data CMSIS_SVD_VARIABLES "" +set_interface_property in_data SVD_ADDRESS_GROUP "" + +add_interface_port in_data in_data data Input 160 +add_interface_port in_data in_data_ready ready Output 1 +add_interface_port in_data in_data_valid valid Input 1 + + +# +# connection point out_token +# +add_interface out_token avalon_streaming start +set_interface_property out_token associatedClock clock_sink +set_interface_property out_token associatedReset reset_sink +set_interface_property out_token dataBitsPerSymbol 8 +set_interface_property out_token errorDescriptor "" +set_interface_property out_token firstSymbolInHighOrderBits true +set_interface_property out_token maxChannel 0 +set_interface_property out_token readyLatency 0 +set_interface_property out_token ENABLED true +set_interface_property out_token EXPORT_OF "" +set_interface_property out_token PORT_NAME_MAP "" +set_interface_property out_token CMSIS_SVD_VARIABLES "" +set_interface_property out_token SVD_ADDRESS_GROUP "" + +add_interface_port out_token out_token data Output 80 +add_interface_port out_token out_token_valid valid Output 1 + + +# +# connection point in_token +# +add_interface in_token avalon_streaming end +set_interface_property in_token associatedClock clock_sink +set_interface_property in_token associatedReset reset_sink +set_interface_property in_token dataBitsPerSymbol 8 +set_interface_property in_token errorDescriptor "" +set_interface_property in_token firstSymbolInHighOrderBits true +set_interface_property in_token maxChannel 0 +set_interface_property in_token readyLatency 0 +set_interface_property in_token ENABLED true +set_interface_property in_token EXPORT_OF "" +set_interface_property in_token PORT_NAME_MAP "" +set_interface_property in_token CMSIS_SVD_VARIABLES "" +set_interface_property in_token SVD_ADDRESS_GROUP "" + +add_interface_port in_token in_token data Input 80 +add_interface_port in_token in_token_valid valid Input 1 + + +# +# connection point mem +# +add_interface mem avalon start +set_interface_property mem addressUnits SYMBOLS +set_interface_property mem associatedClock clock_sink +set_interface_property mem associatedReset reset_sink +set_interface_property mem bitsPerSymbol 8 +set_interface_property mem burstOnBurstBoundariesOnly false +set_interface_property mem burstcountUnits WORDS +set_interface_property mem doStreamReads false +set_interface_property mem doStreamWrites false +set_interface_property mem holdTime 0 +set_interface_property mem linewrapBursts false +set_interface_property mem maximumPendingReadTransactions 0 +set_interface_property mem maximumPendingWriteTransactions 0 +set_interface_property mem readLatency 0 +set_interface_property mem readWaitTime 1 +set_interface_property mem setupTime 0 +set_interface_property mem timingUnits Cycles +set_interface_property mem writeWaitTime 0 +set_interface_property mem ENABLED true +set_interface_property mem EXPORT_OF "" +set_interface_property mem PORT_NAME_MAP "" +set_interface_property mem CMSIS_SVD_VARIABLES "" +set_interface_property mem SVD_ADDRESS_GROUP "" + +add_interface_port mem mem_read read Output 1 +add_interface_port mem mem_write write Output 1 +add_interface_port mem mem_address address Output 32 +add_interface_port mem mem_byteenable byteenable Output 16 +add_interface_port mem mem_readdata readdata Input 128 +add_interface_port mem mem_writedata writedata Output 128 +add_interface_port mem mem_waitrequest waitrequest Input 1 + diff --git a/core_hw.tcl b/core_hw.tcl index 852e6c5..93b6def 100644 --- a/core_hw.tcl +++ b/core_hw.tcl @@ -66,7 +66,7 @@ add_fileset_file writeback.sv SYSTEM_VERILOG PATH rtl/core/control/writeback.sv add_fileset_file ldst.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/ldst.sv add_fileset_file pop.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/pop.sv add_fileset_file sizes.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/sizes.sv -add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache.sv +add_fileset_file cache_ops.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_ops.sv add_fileset_file cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_lockdown.sv add_fileset_file cp15.sv SYSTEM_VERILOG PATH rtl/core/cp15/cp15.sv add_fileset_file cpuid.sv SYSTEM_VERILOG PATH rtl/core/cp15/cpuid.sv diff --git a/platform.qsys b/platform.qsys index 67399ba..d8ed205 100644 --- a/platform.qsys +++ b/platform.qsys @@ -25,6 +25,38 @@ type = "int"; } } + element cache_0 + { + datum _sortIndex + { + value = "20"; + type = "int"; + } + } + element cache_1 + { + datum _sortIndex + { + value = "22"; + type = "int"; + } + } + element cache_2 + { + datum _sortIndex + { + value = "24"; + type = "int"; + } + } + element cache_3 + { + datum _sortIndex + { + value = "26"; + type = "int"; + } + } element clk_0 { datum _sortIndex @@ -41,6 +73,30 @@ type = "int"; } } + element cpu_1 + { + datum _sortIndex + { + value = "21"; + type = "int"; + } + } + element cpu_2 + { + datum _sortIndex + { + value = "23"; + type = "int"; + } + } + element cpu_3 + { + datum _sortIndex + { + value = "25"; + type = "int"; + } + } element hps_0 { datum _sortIndex @@ -73,7 +129,7 @@ type = "int"; } } - element mm_bridge_1 + element mm_bridge { datum _sortIndex { @@ -293,6 +349,18 @@ + + + + + + + + + + + + @@ -302,6 +370,15 @@ + + + + + + + + + @@ -870,13 +947,13 @@ - + @@ -1260,7 +1337,7 @@ @@ -1269,7 +1346,7 @@ @@ -1278,7 +1355,7 @@ @@ -1287,33 +1364,33 @@ - + - + - + - + - + @@ -1321,26 +1398,42 @@ + + + + + + end="mm_bridge.s0"> - + + + + + + + + + + + + + + + + @@ -1360,6 +1453,46 @@ version="20.1" start="pixfmt.avalon_rgb_source" end="pixfifo.avalon_dc_buffer_sink" /> + + + + + + + + + + end="cpu_0.clock_sink" /> + end="cache_0.clock_sink" /> + + + + end="mm_bridge.reset" /> + + + +