From b0cb20496d88cd017c4c51243d16ac3b060cc1d6 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 17 Sep 2022 22:10:39 -0600 Subject: Update project structure to match Verilator Makefile --- Makefile | 36 +++++++++++++------- conspiracion.qsf | 4 +-- rtl/bus/master.sv | 8 ++--- rtl/conspiracion.sv | 90 ------------------------------------------------- rtl/top/conspiracion.sv | 90 +++++++++++++++++++++++++++++++++++++++++++++++++ tb/main.cpp | 19 ----------- tb/top/conspiracion.cpp | 19 +++++++++++ 7 files changed, 139 insertions(+), 127 deletions(-) delete mode 100644 rtl/conspiracion.sv create mode 100644 rtl/top/conspiracion.sv delete mode 100644 tb/main.cpp create mode 100644 tb/top/conspiracion.cpp diff --git a/Makefile b/Makefile index 787efa1..d30e6cb 100644 --- a/Makefile +++ b/Makefile @@ -5,24 +5,36 @@ RTL_DIR := rtl TB_DIR := tb VERILATOR := verilator +RTL_FILES = $(shell find $(RTL_DIR)/ ! -path '$(RTL_DIR)/top/*' -type f -name '*.sv') +RTL_FILES += $(shell find $(TB_DIR)/ ! -path '$(TB_DIR)/top/*' -type f -name '*.sv') +TB_FILES = $(shell find $(TB_DIR)/ ! -path '$(TB_DIR)/top/*' -type f -name '*.cpp') + all: trace clean: rm -rf $(OBJ_DIR) $(VCD_DIR) -trace: exe vcd - cd $(VCD_DIR) && ../$(OBJ_DIR)/V$(TOP) +trace: trace/$(TOP) + +trace/%: exe/% $(VCD_DIR)/% + cd $(VCD_DIR)/$* && ../../$(OBJ_DIR)/$*/V$* + +$(VCD_DIR)/%: + mkdir -p $@ + +exe: exe/$(TOP) -$(VCD_DIR): - @mkdir $(VCD_DIR) +exe/%: $(OBJ_DIR)/%/V%.mk + $(MAKE) -C $(OBJ_DIR)/$* -f V$*.mk -exe: $(OBJ_DIR)/V$(TOP) +.SECONDEXPANSION: -$(OBJ_DIR)/V$(TOP): $(OBJ_DIR)/V$(TOP).mk - $(MAKE) -C $(OBJ_DIR) -f V$(TOP).mk $(MAKEFLAGS) +$(OBJ_DIR)/%.mk: \ + $(RTL_DIR)/top/$$(word 1,$$(subst /, ,$$*)).sv \ + $$(shell find $(RTL_DIR)/top/$$(dir $$*) -type f -name '*.sv' 2>/dev/null) \ + $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f -name '*.sv' 2>/dev/null) \ + $(RTL_FILES) $(TB_FILES) $(TB_DIR)/top/$$(word 1,$$(subst /, ,$$*)).cpp \ + $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f -name '*.cpp' 2>/dev/null) -$(OBJ_DIR)/V$(TOP).mk: $(wildcard $(RTL_DIR)/*.sv) $(wildcard $(TB_DIR)/*.cpp) - $(VERILATOR) \ - --cc --exe --trace \ - -y $(RTL_DIR) --Mdir $(OBJ_DIR) \ - rtl/$(TOP).sv $(wildcard $(TB_DIR)/*.cpp) + mkdir -p $(dir $@) + $(VERILATOR) --cc --exe --trace -y $(RTL_DIR) --Mdir $(dir $@) --top $(word 1,$(subst /, ,$*)) $(patsubst tb/%,../tb/%,$^) diff --git a/conspiracion.qsf b/conspiracion.qsf index b79614d..fd11788 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -56,7 +56,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SYSTEMVERILOG_FILE rtl/conspiracion.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv set_global_assignment -name QIP_FILE platform/synthesis/platform.qip set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0 @@ -212,4 +212,4 @@ set_location_assignment PIN_W20 -to out[7] set_location_assignment PIN_Y21 -to done -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv index 63ea2be..5d8c3a8 100644 --- a/rtl/bus/master.sv +++ b/rtl/bus/master.sv @@ -49,10 +49,10 @@ module bus_master endcase initial begin - ready <= 0; - avl_read <= 0; - avl_write <= 0; - state <= REQUEST; + ready = 0; + avl_read = 0; + avl_write = 0; + state = REQUEST; end endmodule diff --git a/rtl/conspiracion.sv b/rtl/conspiracion.sv deleted file mode 100644 index 83e7d10..0000000 --- a/rtl/conspiracion.sv +++ /dev/null @@ -1,90 +0,0 @@ -module conspiracion -( - input wire clk_clk, - output wire [12:0] memory_mem_a, - output wire [2:0] memory_mem_ba, - output wire memory_mem_ck, - output wire memory_mem_ck_n, - output wire memory_mem_cke, - output wire memory_mem_cs_n, - output wire memory_mem_ras_n, - output wire memory_mem_cas_n, - output wire memory_mem_we_n, - output wire memory_mem_reset_n, - inout wire [7:0] memory_mem_dq, - inout wire memory_mem_dqs, - inout wire memory_mem_dqs_n, - output wire memory_mem_odt, - output wire memory_mem_dm, - input wire memory_oct_rzqin, - input wire reset_reset_n, - - input logic dir, clr, mov, add, io, - output logic[7:0] out, - output logic done -); - - enum { - IDLE, - IO, - RELEASE - } state; - - logic[29:0] addr; - logic[31:0] data_rd, data_rw; - logic ready, write, start; - - logic [7:0] leds; - - platform plat - ( - .master_0_core_addr(addr), - .master_0_core_data_rd(data_rd), - .master_0_core_data_rw(data_rw), - .master_0_core_ready(ready), - .master_0_core_write(write), - .master_0_core_start(start), - .* - ); - - initial begin - addr <= 0; - start <= 0; - state <= IDLE; - done <= 0; - end - - assign data_rw[7:0] = out; - assign write = dir; - - always @(posedge clk_clk) unique case(state) - IDLE: begin - state <= RELEASE; - - if(~clr) - out <= 0; - else if(~mov) - addr <= dir ? addr + 1 : addr - 1; - else if(~add) - out <= dir ? out + 1 : out - 1; - else if(~io) begin - start <= 1; - state <= IO; - end - end - - IO: begin - done <= 1; - start <= 0; - if(ready) begin - if(~dir) out <= data_rd[7:0]; - state <= RELEASE; - end - end - - RELEASE: begin - done <= ~io; - if(clr & mov & add & io) state <= IDLE; - end - endcase -endmodule diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv new file mode 100644 index 0000000..83e7d10 --- /dev/null +++ b/rtl/top/conspiracion.sv @@ -0,0 +1,90 @@ +module conspiracion +( + input wire clk_clk, + output wire [12:0] memory_mem_a, + output wire [2:0] memory_mem_ba, + output wire memory_mem_ck, + output wire memory_mem_ck_n, + output wire memory_mem_cke, + output wire memory_mem_cs_n, + output wire memory_mem_ras_n, + output wire memory_mem_cas_n, + output wire memory_mem_we_n, + output wire memory_mem_reset_n, + inout wire [7:0] memory_mem_dq, + inout wire memory_mem_dqs, + inout wire memory_mem_dqs_n, + output wire memory_mem_odt, + output wire memory_mem_dm, + input wire memory_oct_rzqin, + input wire reset_reset_n, + + input logic dir, clr, mov, add, io, + output logic[7:0] out, + output logic done +); + + enum { + IDLE, + IO, + RELEASE + } state; + + logic[29:0] addr; + logic[31:0] data_rd, data_rw; + logic ready, write, start; + + logic [7:0] leds; + + platform plat + ( + .master_0_core_addr(addr), + .master_0_core_data_rd(data_rd), + .master_0_core_data_rw(data_rw), + .master_0_core_ready(ready), + .master_0_core_write(write), + .master_0_core_start(start), + .* + ); + + initial begin + addr <= 0; + start <= 0; + state <= IDLE; + done <= 0; + end + + assign data_rw[7:0] = out; + assign write = dir; + + always @(posedge clk_clk) unique case(state) + IDLE: begin + state <= RELEASE; + + if(~clr) + out <= 0; + else if(~mov) + addr <= dir ? addr + 1 : addr - 1; + else if(~add) + out <= dir ? out + 1 : out - 1; + else if(~io) begin + start <= 1; + state <= IO; + end + end + + IO: begin + done <= 1; + start <= 0; + if(ready) begin + if(~dir) out <= data_rd[7:0]; + state <= RELEASE; + end + end + + RELEASE: begin + done <= ~io; + if(clr & mov & add & io) state <= IDLE; + end + endcase +endmodule diff --git a/tb/main.cpp b/tb/main.cpp deleted file mode 100644 index d4bdbcb..0000000 --- a/tb/main.cpp +++ /dev/null @@ -1,19 +0,0 @@ -#include -#include - -#include "Vconspiracion.h" - -int main(int argc, char **argv) -{ - Verilated::commandArgs(argc, argv); // Remember args - Verilated::traceEverOn(true); - - Vconspiracion top; - // Do not instead make Vtop as a file-scope static - // variable, as the "C++ static initialization order fiasco" - // may cause a crash - - top.eval(); - - top.final(); -} diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp new file mode 100644 index 0000000..d4bdbcb --- /dev/null +++ b/tb/top/conspiracion.cpp @@ -0,0 +1,19 @@ +#include +#include + +#include "Vconspiracion.h" + +int main(int argc, char **argv) +{ + Verilated::commandArgs(argc, argv); // Remember args + Verilated::traceEverOn(true); + + Vconspiracion top; + // Do not instead make Vtop as a file-scope static + // variable, as the "C++ static initialization order fiasco" + // may cause a crash + + top.eval(); + + top.final(); +} -- cgit v1.2.3