From 8d590a8a7178659278ea44424d8456be16a006ad Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 6 Nov 2022 15:56:06 -0600
Subject: Clean-up control.sv

---
 rtl/core/control/control.sv   | 8 --------
 rtl/core/control/data.sv      | 2 +-
 rtl/core/control/select.sv    | 5 ++++-
 rtl/core/control/writeback.sv | 9 +++++++--
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index e8a1a69..056606d 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -54,8 +54,6 @@ module core_control
 	                       coproc
 );
 
-	assign reg_mode = `MODE_SVC; //TODO
-
 	ctrl_cycle cycle, next_cycle;
 
 	core_control_cycles ctrl_cycles
@@ -131,10 +129,4 @@ module core_control
 		.*
 	);
 
-	always_ff @(posedge clk)
-		wb_alu_flags <= alu_flags;
-
-	initial
-		wb_alu_flags = 4'b0000;
-
 endmodule
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index cc83336..4965ec3 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -64,7 +64,7 @@ module core_control_data
 		endcase
 	end
 
-	always @(posedge clk)
+	always_ff @(posedge clk)
 		unique0 case(next_cycle)
 			ISSUE:
 				if(issue) begin
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index a073e24..ea9850b 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -16,11 +16,14 @@ module core_control_select
 	                   final_rd,
 
 	output reg_num     ra,
-	                   rb
+	                   rb,
+	output psr_mode    reg_mode
 );
 
 	reg_num r_shift;
 
+	assign reg_mode = `MODE_SVC; //TODO
+
 	always_ff @(posedge clk)
 		unique0 case(next_cycle)
 			ISSUE:
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 021d494..15b17ee 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -13,6 +13,7 @@ module core_control_writeback
 	                       mem_data_rd,
 	                       vector,
 	                       q_alu,
+	input  psr_flags       alu_flags,
 	input  reg_num         ra,
 	                       popped,
 	input  logic           pop_valid,
@@ -26,10 +27,13 @@ module core_control_writeback
 	                       final_writeback,
 	                       update_flags,
 	                       final_update_flags,
-	output word            wr_value
+	output word            wr_value,
+	output psr_flags       wb_alu_flags
 );
 
-	always @(posedge clk) begin
+	always_ff @(posedge clk) begin
+		wb_alu_flags <= alu_flags;
+
 		unique0 case(next_cycle)
 			TRANSFER:
 				if(mem_ready)
@@ -128,6 +132,7 @@ module core_control_writeback
 		final_update_flags = 0;
 
 		wr_value = 0;
+		wb_alu_flags = {$bits(wb_alu_flags){1'b0}};
 	end
 
 endmodule
-- 
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