From 88a1fbece18c06dc0bbb3dcc63bcad87f7040f2c Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sat, 9 Mar 2024 10:41:24 -0600
Subject: mk/verilator: add output line to sim

---
 mk/verilator.mk | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/mk/verilator.mk b/mk/verilator.mk
index 2692863..cc63ea1 100644
--- a/mk/verilator.mk
+++ b/mk/verilator.mk
@@ -26,7 +26,9 @@ define target/sim/rules
   .PHONY: $$(rule_top_path)/sim
 
   $$(rule_top_path)/sim: $$(vtop_exe)
-	$$<
+	$$(call run,RUN) $$<
+
+  $(call target_entrypoint,$$(rule_top_path)/sim)
 endef
 
 define prepare_verilator_target
-- 
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