From 79b3a4f57f269f6243177a1bf0073646fef61413 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 24 Sep 2023 23:40:33 -0600 Subject: sim: fix silent fopen() fail --- Makefile | 6 +++--- nix/flake.nix | 3 ++- sim/gdbstub.py | 5 ++++- sim/sim.py | 4 +++- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 8f5399d..1035ed3 100644 --- a/Makefile +++ b/Makefile @@ -7,8 +7,8 @@ SIM_DIR := sim TB_SIM_DIR := $(TB_DIR)/sim SIM_OBJ_DIR := $(OBJ_DIR)/$(TOP)/sim VERILATOR := verilator -CROSS_CC := arm-none-eabi-gcc -CROSS_OBJCOPY := arm-none-eabi-objcopy +CROSS_CC := $(CROSS_COMPILE)gcc +CROSS_OBJCOPY := $(CROSS_COMPILE)objcopy CROSS_CFLAGS := -O3 -Wall -Wextra -Werror CROSS_LDFLAGS := @@ -35,7 +35,7 @@ sim/%: $(SIM_DIR)/sim.py $(TB_SIM_DIR)/%.py exe/$(TOP) $(SIM_OBJ_DIR)/%.bin @$< $(TB_SIM_DIR)/$*.py $(OBJ_DIR)/$(TOP)/V$(TOP) $(SIM_OBJ_DIR)/$*.bin vmlaunch: $(SIM_DIR)/sim.py $(SIM_DIR)/gdbstub.py exe/$(TOP) - @$< $(SIM_DIR)/gdbstub.py $(OBJ_DIR)/$(TOP)/V$(TOP) u-boot/build/u-boot-dtb.bin + @$< $(SIM_DIR)/gdbstub.py $(OBJ_DIR)/$(TOP)/V$(TOP) u-boot/build/taller/u-boot-dtb.bin $(SIM_OBJ_DIR)/%.bin: $(SIM_OBJ_DIR)/% $(CROSS_OBJCOPY) -O binary --only-section=._img $< $@ diff --git a/nix/flake.nix b/nix/flake.nix index 582a15d..5de1f31 100644 --- a/nix/flake.nix +++ b/nix/flake.nix @@ -121,6 +121,7 @@ ]; shellHook = '' + export CROSS_COMPILE=arm-unknown-linux-gnueabi- export MAKEFLAGS="AR=gcc-ar" export CXXFLAGS="-O3 -flto $(pkg-config --cflags sdl2 ncursesw)" export LDFLAGS="-O3 -flto $(pkg-config --libs sdl2 ncursesw)" @@ -149,7 +150,7 @@ ]; shellHook = '' - export CROSS_COMPILE=arm-none-eabi- + export CROSS_COMPILE=arm-unknown-linux-gnueabi- export MAKEFLAGS="ARCH=arm O=build/taller LOADADDR=0x8000" ''; }; diff --git a/sim/gdbstub.py b/sim/gdbstub.py index ccddab9..e7791bc 100644 --- a/sim/gdbstub.py +++ b/sim/gdbstub.py @@ -23,7 +23,10 @@ def fatal(): def do_output(text): if text is None: return not is_halted() - elif not client: + + print(text, file=sys.stderr, end='') + + if not client: return False reply(b'O' + hexout(text.encode('ascii'))) diff --git a/sim/sim.py b/sim/sim.py index b45ca7e..5f64d43 100755 --- a/sim/sim.py +++ b/sim/sim.py @@ -222,6 +222,7 @@ def exit(*, success): f'{color}Test \'{COLOR_YELLOW}{test_name}{COLOR_RESET}{color}\' ' + f'{status}{COLOR_RESET}') + flush_out() sys.exit(0 if success else 1) def dump_regs(): @@ -393,7 +394,7 @@ exec_args.append(f'+verilator+seed+{seed}') if not os.getenv('SIM_PULLX', 0): exec_args.append('+verilator+rand+reset+2') -process = subprocess.Popen(exec_args, pass_fds=(target_fd,)) +process = subprocess.Popen(exec_args, pass_fds=(target_fd,), stderr=subprocess.PIPE) target_end.close() in_regs = False @@ -462,6 +463,7 @@ while not done: process.wait(timeout=1) if process.returncode != 0: + out(f'{COLOR_RED}{verilated} exited with status {process.returncode}{COLOR_RESET}') exit(success=False) if final := module_get('final'): -- cgit v1.2.3