From 601835e33298015cf49f0ab33a7ef3d61b003ad9 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sat, 24 Sep 2022 21:41:46 -0600
Subject: Implement initial decoder

---
 rtl/core/arm810.sv        | 12 +++++++++
 rtl/core/decode/conds.sv  | 39 ++++++++++++++++++++++++++++
 rtl/core/decode/decode.sv | 65 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 116 insertions(+)
 create mode 100644 rtl/core/decode/conds.sv
 create mode 100644 rtl/core/decode/decode.sv

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index cbb0244..4c72fa2 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -1,3 +1,5 @@
+`include "core/uarch.sv"
+
 module arm810
 (
 	input  logic       clk,
@@ -14,6 +16,9 @@ module arm810
 	logic[31:0] insn;
 	logic[29:0] insn_pc;
 
+	psr_flags flags;
+	assign flags = 4'b1010;
+
 	core_fetch #(.PREFETCH_ORDER(2)) fetch
 	(
 		.flush(prefetch_flush),
@@ -24,4 +29,11 @@ module arm810
 		.*
 	);
 
+	//TODO
+	logic execute, undefined;
+	core_decode decode
+	(
+		.*
+	);
+
 endmodule
diff --git a/rtl/core/decode/conds.sv b/rtl/core/decode/conds.sv
new file mode 100644
index 0000000..3eef925
--- /dev/null
+++ b/rtl/core/decode/conds.sv
@@ -0,0 +1,39 @@
+`include "core/isa.sv"
+`include "core/psr.sv"
+
+module core_decode_conds
+(
+	input  logic[3:0] cond,
+	input  psr_flags  flags,
+	output logic      execute,
+	                  undefined
+);
+
+	always_comb begin
+		undefined = 0;
+
+		unique case(cond)
+			`COND_EQ: execute =  flags.z;
+			`COND_NE: execute = ~flags.z;
+			`COND_HS: execute =  flags.c;
+			`COND_LO: execute = ~flags.c;
+			`COND_MI: execute =  flags.n;
+			`COND_PL: execute = ~flags.n;
+			`COND_VS: execute =  flags.v;
+			`COND_VC: execute = ~flags.v;
+			`COND_HI: execute =  flags.c  & ~flags.z;
+			`COND_LS: execute = ~flags.c  |  flags.z;
+			`COND_GE: execute =  flags.n ~^  flags.v;
+			`COND_LT: execute =  flags.n  ^  flags.v;
+			`COND_GT: execute = ~flags.z  & (flags.n ~^ flags.v);
+			`COND_LE: execute =  flags.z  | (flags.n  ^ flags.v);
+			`COND_AL: execute = 1;
+
+			`COND_UD: begin
+				execute = 1'bx;
+				undefined = 1;
+			end
+		endcase
+	end
+
+endmodule
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
new file mode 100644
index 0000000..3470665
--- /dev/null
+++ b/rtl/core/decode/decode.sv
@@ -0,0 +1,65 @@
+`include "core/isa.sv"
+`include "core/psr.sv"
+`include "core/uarch.sv"
+
+module core_decode
+(
+	input  logic[31:0] insn,
+	input  psr_flags   flags,
+	output logic       execute,
+	                   undefined
+);
+
+	logic cond_undefined;
+
+	//TODO
+	logic link;
+	logic[29:0] offset;
+	core_decode_conds conds
+	(
+		.cond(insn `FIELD_COND),
+		.undefined(cond_undefined),
+		.*
+	);
+
+	logic branch_link;
+	logic[29:0] branch_offset;
+
+	core_decode_branch branch
+	(
+		.*
+	);
+
+	//TODO
+	alu_op op;
+	reg_num rn, rd;
+	logic writeback, update_flags, restore_spsr, zero_fst, negate_fst, negate_snd, carry_in;
+	core_decode_data data
+	(
+		.*
+	);
+
+	always_comb begin
+		undefined = cond_undefined;
+
+		priority case(insn `FIELD_OP) inside
+			`GROUP_B: ;
+
+			`GROUP_ALU: begin
+			end
+
+			`INSN_MUL: ;
+			`GROUP_BIGMUL: ;
+			`GROUP_LDST_MISC: ;
+			`GROUP_LDST_MULT: ;
+			`GROUP_SWP: ;
+			`GROUP_CP: ;
+			`INSN_MRS: ;
+			`GROUP_MSR: ;
+			`INSN_SWI: ;
+
+			default: undefined = 1;
+		endcase
+	end
+
+endmodule
-- 
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