From 4ef4190e67534168e1e64b810a09c0cd1338e2a9 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 2 Nov 2022 23:19:48 -0600 Subject: Move bus/master.sv to bus_master.sv --- conspiracion_bus_master_hw.tcl | 6 ++-- rtl/bus/master.sv | 63 ------------------------------------------ rtl/bus_master.sv | 63 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+), 66 deletions(-) delete mode 100644 rtl/bus/master.sv create mode 100644 rtl/bus_master.sv diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl index 3695140..dadceca 100644 --- a/conspiracion_bus_master_hw.tcl +++ b/conspiracion_bus_master_hw.tcl @@ -1,11 +1,11 @@ # TCL File Generated by Component Editor 20.1 -# Sun Oct 16 06:18:24 GMT 2022 +# Thu Nov 03 05:18:16 GMT 2022 # DO NOT MODIFY # # conspiracion_bus_master "Toplevel bus master" v1.0 -# 2022.10.16.06:18:24 +# 2022.11.03.05:18:16 # # @@ -39,7 +39,7 @@ add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL bus_master set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false -add_fileset_file master.sv SYSTEM_VERILOG PATH rtl/bus/master.sv TOP_LEVEL_FILE +add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/bus_master.sv # diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv deleted file mode 100644 index e4a76d2..0000000 --- a/rtl/bus/master.sv +++ /dev/null @@ -1,63 +0,0 @@ -module bus_master -( - input logic clk, - rst, - - input logic[29:0] addr, - input logic start, - write, - output logic ready, - output logic[31:0] data_rd, - input logic[31:0] data_wr, - - output logic[31:0] avl_address, - output logic avl_read, - avl_write, - input logic[31:0] avl_readdata, - output logic[31:0] avl_writedata, - input logic avl_waitrequest, - output logic[3:0] avl_byteenable -); - - enum { - IDLE, - WAIT - } state; - - assign data_rd = avl_readdata; - assign avl_byteenable = 4'b1111; //TODO - - always_comb - unique case(state) - IDLE: ready = 0; - WAIT: ready = !avl_waitrequest; - endcase - - always_ff @(posedge clk) begin - unique case(state) - IDLE: begin - avl_read <= 0; - avl_write <= 0; - end - - WAIT: - if(!start) - state <= IDLE; - endcase - - if(!avl_waitrequest && start) begin - avl_address <= {addr, 2'b00}; - avl_read <= ~write; - avl_write <= write; - avl_writedata <= data_wr; - state <= WAIT; - end - end - - initial begin - state = IDLE; - avl_read = 0; - avl_write = 0; - end - -endmodule diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv new file mode 100644 index 0000000..e4a76d2 --- /dev/null +++ b/rtl/bus_master.sv @@ -0,0 +1,63 @@ +module bus_master +( + input logic clk, + rst, + + input logic[29:0] addr, + input logic start, + write, + output logic ready, + output logic[31:0] data_rd, + input logic[31:0] data_wr, + + output logic[31:0] avl_address, + output logic avl_read, + avl_write, + input logic[31:0] avl_readdata, + output logic[31:0] avl_writedata, + input logic avl_waitrequest, + output logic[3:0] avl_byteenable +); + + enum { + IDLE, + WAIT + } state; + + assign data_rd = avl_readdata; + assign avl_byteenable = 4'b1111; //TODO + + always_comb + unique case(state) + IDLE: ready = 0; + WAIT: ready = !avl_waitrequest; + endcase + + always_ff @(posedge clk) begin + unique case(state) + IDLE: begin + avl_read <= 0; + avl_write <= 0; + end + + WAIT: + if(!start) + state <= IDLE; + endcase + + if(!avl_waitrequest && start) begin + avl_address <= {addr, 2'b00}; + avl_read <= ~write; + avl_write <= write; + avl_writedata <= data_wr; + state <= WAIT; + end + end + + initial begin + state = IDLE; + avl_read = 0; + avl_write = 0; + end + +endmodule -- cgit v1.2.3