From 044558e53d50ebd053abc76930723c9d7f606569 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 15 Nov 2022 16:25:41 -0600 Subject: Replace vga_controller with streaming Altera IP --- conspiracion.qsf | 59 ++++++------ platform.qsys | 238 ++++++++++++++++++++++++++++++++++++++++++++---- rtl/top/conspiracion.sv | 24 +++-- rtl/vga.sv | 3 + tb/platform.sv | 18 ++-- 5 files changed, 276 insertions(+), 66 deletions(-) diff --git a/conspiracion.qsf b/conspiracion.qsf index b667d1a..1c4a47b 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -120,35 +120,35 @@ set_location_assignment PIN_W19 -to pio_leds[5] set_location_assignment PIN_Y19 -to pio_leds[6] set_location_assignment PIN_W20 -to pio_leds[7] -set_location_assignment PIN_A11 -to vga_controller_0_dac_clk -set_location_assignment PIN_B11 -to vga_controller_0_dac_hsync -set_location_assignment PIN_D11 -to vga_controller_0_dac_vsync -set_location_assignment PIN_F10 -to vga_controller_0_dac_blank_n -set_location_assignment PIN_C10 -to vga_controller_0_dac_sync_n -set_location_assignment PIN_A13 -to vga_controller_0_dac_r[0] -set_location_assignment PIN_C13 -to vga_controller_0_dac_r[1] -set_location_assignment PIN_E13 -to vga_controller_0_dac_r[2] -set_location_assignment PIN_B12 -to vga_controller_0_dac_r[3] -set_location_assignment PIN_C12 -to vga_controller_0_dac_r[4] -set_location_assignment PIN_D12 -to vga_controller_0_dac_r[5] -set_location_assignment PIN_E12 -to vga_controller_0_dac_r[6] -set_location_assignment PIN_F13 -to vga_controller_0_dac_r[7] -set_location_assignment PIN_J9 -to vga_controller_0_dac_g[0] -set_location_assignment PIN_J10 -to vga_controller_0_dac_g[1] -set_location_assignment PIN_H12 -to vga_controller_0_dac_g[2] -set_location_assignment PIN_G10 -to vga_controller_0_dac_g[3] -set_location_assignment PIN_G11 -to vga_controller_0_dac_g[4] -set_location_assignment PIN_G12 -to vga_controller_0_dac_g[5] -set_location_assignment PIN_F11 -to vga_controller_0_dac_g[6] -set_location_assignment PIN_E11 -to vga_controller_0_dac_g[7] -set_location_assignment PIN_B13 -to vga_controller_0_dac_b[0] -set_location_assignment PIN_G13 -to vga_controller_0_dac_b[1] -set_location_assignment PIN_H13 -to vga_controller_0_dac_b[2] -set_location_assignment PIN_F14 -to vga_controller_0_dac_b[3] -set_location_assignment PIN_H14 -to vga_controller_0_dac_b[4] -set_location_assignment PIN_F15 -to vga_controller_0_dac_b[5] -set_location_assignment PIN_G15 -to vga_controller_0_dac_b[6] -set_location_assignment PIN_J14 -to vga_controller_0_dac_b[7] +set_location_assignment PIN_A11 -to vga_dac_clk +set_location_assignment PIN_B11 -to vga_dac_hsync +set_location_assignment PIN_D11 -to vga_dac_vsync +set_location_assignment PIN_F10 -to vga_dac_blank_n +set_location_assignment PIN_C10 -to vga_dac_sync_n +set_location_assignment PIN_A13 -to vga_dac_r[0] +set_location_assignment PIN_C13 -to vga_dac_r[1] +set_location_assignment PIN_E13 -to vga_dac_r[2] +set_location_assignment PIN_B12 -to vga_dac_r[3] +set_location_assignment PIN_C12 -to vga_dac_r[4] +set_location_assignment PIN_D12 -to vga_dac_r[5] +set_location_assignment PIN_E12 -to vga_dac_r[6] +set_location_assignment PIN_F13 -to vga_dac_r[7] +set_location_assignment PIN_J9 -to vga_dac_g[0] +set_location_assignment PIN_J10 -to vga_dac_g[1] +set_location_assignment PIN_H12 -to vga_dac_g[2] +set_location_assignment PIN_G10 -to vga_dac_g[3] +set_location_assignment PIN_G11 -to vga_dac_g[4] +set_location_assignment PIN_G12 -to vga_dac_g[5] +set_location_assignment PIN_F11 -to vga_dac_g[6] +set_location_assignment PIN_E11 -to vga_dac_g[7] +set_location_assignment PIN_B13 -to vga_dac_b[0] +set_location_assignment PIN_G13 -to vga_dac_b[1] +set_location_assignment PIN_H13 -to vga_dac_b[2] +set_location_assignment PIN_F14 -to vga_dac_b[3] +set_location_assignment PIN_H14 -to vga_dac_b[4] +set_location_assignment PIN_F15 -to vga_dac_b[5] +set_location_assignment PIN_G15 -to vga_dac_b[6] +set_location_assignment PIN_J14 -to vga_dac_b[7] set_location_assignment PIN_AK14 -to vram_wire_addr[0] set_location_assignment PIN_AH14 -to vram_wire_addr[1] @@ -350,4 +350,5 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE bus_test.stp set_global_assignment -name SIGNALTAP_FILE bus_test.stp + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/platform.qsys b/platform.qsys index 73ef6e6..30158b8 100644 --- a/platform.qsys +++ b/platform.qsys @@ -37,7 +37,7 @@ { datum _sortIndex { - value = "10"; + value = "9"; type = "int"; } } @@ -65,6 +65,35 @@ type = "int"; } } + element pixdma + { + datum _sortIndex + { + value = "13"; + type = "int"; + } + } + element pixfifo + { + datum _sortIndex + { + value = "15"; + type = "int"; + } + } + element pixfmt + { + datum _sortIndex + { + value = "14"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } element platform { datum _originalDeviceFamily @@ -109,7 +138,7 @@ { datum _sortIndex { - value = "11"; + value = "10"; type = "int"; } } @@ -121,11 +150,24 @@ type = "int"; } } - element vga_controller_0 + element vga { datum _sortIndex { - value = "9"; + value = "12"; + type = "int"; + } + datum sopceditor_expanded + { + value = "0"; + type = "boolean"; + } + } + element video_pll_0 + { + datum _sortIndex + { + value = "11"; type = "int"; } } @@ -180,8 +222,8 @@ type="clock" dir="start" /> @@ -789,6 +831,42 @@ + + + + + + + + + + + + + + + + + + + + + + + + @@ -906,7 +984,7 @@ - + @@ -1021,10 +1099,33 @@ + name="vga" + kind="altera_up_avalon_video_vga_controller" + version="18.0" + enabled="1"> + + + + + + + + + + + 5MP Digital Camera (THDB_D5M) + + + + 7" LCD on VEEK-MT and MTL/MTL2 Modules + + + + + start="master_0.avalon_master_1_1" + end="pixdma.avalon_control_slave"> - + + + + + + + + + + + + + + + + + + + + + @@ -1150,11 +1287,31 @@ + + + + + start="sys_sdram_pll_0.sys_clk" + end="vram.clk" /> + end="pixdma.clk" /> + + + + + + start="sys_sdram_pll_0.reset_source" + end="vram.reset" /> + + end="pixdma.reset" /> + + + diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 62eb9c1..450af54 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -30,14 +30,14 @@ module conspiracion output wire vram_wire_ras_n, output wire vram_wire_we_n, output wire [7:0] pio_leds, - output wire vga_controller_0_dac_clk, - output wire vga_controller_0_dac_hsync, - output wire vga_controller_0_dac_vsync, - output wire vga_controller_0_dac_blank_n, - output wire vga_controller_0_dac_sync_n, - output wire [7:0] vga_controller_0_dac_r, - output wire [7:0] vga_controller_0_dac_g, - output wire [7:0] vga_controller_0_dac_b + output wire vga_dac_clk, + output wire vga_dac_hsync, + output wire vga_dac_vsync, + output wire vga_dac_blank_n, + output wire vga_dac_sync_n, + output wire [7:0] vga_dac_r, + output wire [7:0] vga_dac_g, + output wire [7:0] vga_dac_b ); logic[29:0] addr; @@ -93,6 +93,14 @@ module conspiracion .pll_0_reset_reset(0), //TODO: reset controller, algún día .pio_0_external_connection_export(pio_leds), .sys_sdram_pll_0_sdram_clk_clk(vram_wire_clk), + .vga_dac_CLK(vga_dac_clk), + .vga_dac_HS(vga_dac_hsync), + .vga_dac_VS(vga_dac_vsync), + .vga_dac_BLANK(vga_dac_blank_n), + .vga_dac_SYNC(vga_dac_sync_n), + .vga_dac_R(vga_dac_r), + .vga_dac_G(vga_dac_g), + .vga_dac_B(vga_dac_b), .* ); diff --git a/rtl/vga.sv b/rtl/vga.sv index d720578..e3ba04b 100644 --- a/rtl/vga.sv +++ b/rtl/vga.sv @@ -120,6 +120,9 @@ module vga B: current = read_b; endcase + if(!next_active) + current = {$bits(current){1'b0}}; + if(x != H_TOTAL - 1) begin next_x = x + 1; next_y = y; diff --git a/tb/platform.sv b/tb/platform.sv index 5def85f..5fcb9f2 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -28,7 +28,7 @@ module platform input wire memory_oct_rzqin, // .oct_rzqin output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export input wire pll_0_reset_reset, - output wire pll_0_outclk3_clk, // pll_0_outclk3.clk + output wire sys_sdram_pll_0_sdram_clk_clk, input wire reset_reset_n /*verilator public*/,// reset.reset_n output wire [12:0] vram_wire_addr, // vram_wire.addr output wire [1:0] vram_wire_ba, // .ba @@ -39,14 +39,14 @@ module platform output wire [1:0] vram_wire_dqm, // .dqm output wire vram_wire_ras_n, // .ras_n output wire vram_wire_we_n, // .we_n - output wire vga_controller_0_dac_clk, // vga_controller_0_dac.clk - output wire vga_controller_0_dac_hsync, // .hsync - output wire vga_controller_0_dac_vsync, // .vsync - output wire vga_controller_0_dac_blank_n, // .blank_n - output wire vga_controller_0_dac_sync_n, // .sync_n - output wire [7:0] vga_controller_0_dac_r, // .r - output wire [7:0] vga_controller_0_dac_g, // .g - output wire [7:0] vga_controller_0_dac_b // .b + output wire vga_dac_CLK, // vga_dac.CLK + output wire vga_dac_HS, // .HS + output wire vga_dac_VS, // .VS + output wire vga_dac_BLANK, // .BLANK + output wire vga_dac_SYNC, // .SYNC + output wire [7:0] vga_dac_R, // .R + output wire [7:0] vga_dac_G, // .G + output wire [7:0] vga_dac_B // .B ); logic[31:0] avl_address /*verilator public*/; -- cgit v1.2.3