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AgeCommit message (Expand)Author
2022-11-20Add tick, bail signals to simulated Avalon slavesAlejandro Soto
2022-11-19Implement JTAG-UART inputAlejandro Soto
2022-11-19Implement interval timer simulationAlejandro Soto
2022-11-17Finish simulationAlejandro Soto
2022-11-17Fix simAlejandro Soto
2022-11-17Implement sim test: descifradorAlejandro Soto
2022-11-17Bug fixesJulianCamacho
2022-11-16Gracefully exit when Avalon assertions fail during simulationAlejandro Soto
2022-11-16Implement JTAG-UART tx emulationAlejandro Soto
2022-11-16Implement bx lrAlejandro Soto
2022-11-16Implement privilege escalationAlejandro Soto
2022-11-16Implement psr read/write logicAlejandro Soto
2022-11-16Add sim test: subwordAlejandro Soto
2022-11-15Implemente byte-enable signal in storesAlejandro Soto
2022-11-15Replace vga_controller with streaming Altera IPAlejandro Soto
2022-11-14Implement VGA simulationAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-13Route cpu_rst_n signal through bus masterAlejandro Soto
2022-11-13Add reset debounceAlejandro Soto
2022-11-13Hardwire PLL reset to groundAlejandro Soto
2022-11-10Implement support for predictable x-values in simAlejandro Soto
2022-11-09Improve sdram sim testAlejandro Soto
2022-11-09Implement initial state randomization in simAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-11-09Add reset signal to bus masterAlejandro Soto
2022-11-09Fix bus protocol errors in bus masterAlejandro Soto
2022-11-09Update fetch, decode testbenchesAlejandro Soto
2022-11-08Fix handling of multi-cycle Avalon waitrequest states in bus masterAlejandro Soto
2022-11-08Add sim: sdramAlejandro Soto
2022-11-07Añade testbench para fetch y decodeJulianCamacho
2022-11-07Adding decode instructions for testJulianCamacho
2022-11-07Adding decode testJulianCamacho
2022-11-07Add test sim: modeswitchAlejandro Soto
2022-11-07Improve mult simAlejandro Soto
2022-11-06Export PSRs to simulationAlejandro Soto
2022-11-06Add multiplier unitAlejandro Soto
2022-11-03Add toplevel wires for VGA DACAlejandro Soto
2022-11-02Add bus master forward signals: irq, cpu_clkAlejandro Soto
2022-11-02Add new toplevel signalsAlejandro Soto
2022-10-31Show simulator output in sim testbenchesAlejandro Soto
2022-10-31Merge branch 'mul'Alejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-25Implement explicit sim state dumpAlejandro Soto
2022-10-25Add sim test: tarea2Alejandro Soto
2022-10-23Add sim test: shiftsAlejandro Soto
2022-10-23Add sim test: stackAlejandro Soto
2022-10-18Add sim test: control_flowAlejandro Soto
2022-10-18Add sim test: multAlejandro Soto
2022-10-18Print simulator command line on test failureAlejandro Soto
2022-10-18Support skipping testsAlejandro Soto
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