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AgeCommit message (Expand)Author
2022-11-03Add toplevel wires for VGA DACAlejandro Soto
2022-11-02Add bus master forward signals: irq, cpu_clkAlejandro Soto
2022-11-02Add new toplevel signalsAlejandro Soto
2022-10-31Show simulator output in sim testbenchesAlejandro Soto
2022-10-31Merge branch 'mul'Alejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-25Implement explicit sim state dumpAlejandro Soto
2022-10-25Add sim test: tarea2Alejandro Soto
2022-10-23Add sim test: shiftsAlejandro Soto
2022-10-23Add sim test: stackAlejandro Soto
2022-10-18Add sim test: control_flowAlejandro Soto
2022-10-18Add sim test: multAlejandro Soto
2022-10-18Print simulator command line on test failureAlejandro Soto
2022-10-18Support skipping testsAlejandro Soto
2022-10-18Support program counter in --dump-regsAlejandro Soto
2022-10-18Implement register initialization in simAlejandro Soto
2022-10-17Break false dependency on r0 for MOV/MVNAlejandro Soto
2022-10-17Improve sim.py outputAlejandro Soto
2022-10-16Implement register dumpsAlejandro Soto
2022-10-16Add C simulation testbenchAlejandro Soto
2022-10-16Add original simulation testbenchAlejandro Soto
2022-10-16Implement simulation testbenchesAlejandro Soto
2022-10-15Rework bus architectureAlejandro Soto
2022-09-27Add simple loop execution testbenchAlejandro Soto
2022-09-25Rename HPS SDRAM testbench fileAlejandro Soto
2022-09-18Rename data_rw to data_wr in bus masterAlejandro Soto
2022-09-18Fix public_flat_rw signalsAlejandro Soto
2022-09-18Fix memory simulationAlejandro Soto
2022-09-18Implement Avalon memory module for simulationAlejandro Soto
2022-09-18Update testbenchAlejandro Soto
2022-09-18Add Avalon-MM emulatorAlejandro Soto
2022-09-17Update project structure to match Verilator MakefileAlejandro Soto
2022-09-01Initial commitAlejandro Soto
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