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2022-11-14Implement VGA simulationAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-13Add reset debounceAlejandro Soto
2022-11-09Implement initial state randomization in simAlejandro Soto
2022-11-09Update fetch, decode testbenchesAlejandro Soto
2022-11-07Añade testbench para fetch y decodeJulianCamacho
2022-11-07Adding decode instructions for testJulianCamacho
2022-11-07Adding decode testJulianCamacho
2022-11-06Export PSRs to simulationAlejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-18Support program counter in --dump-regsAlejandro Soto
2022-10-18Implement register initialization in simAlejandro Soto
2022-10-16Implement register dumpsAlejandro Soto
2022-10-16Implement simulation testbenchesAlejandro Soto
2022-09-27Add simple loop execution testbenchAlejandro Soto
2022-09-25Rename HPS SDRAM testbench fileAlejandro Soto
2022-09-18Fix memory simulationAlejandro Soto
2022-09-18Update testbenchAlejandro Soto
2022-09-17Update project structure to match Verilator MakefileAlejandro Soto
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 14:01:11 +0000