| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-10-18 | Print simulator command line on test failure | Alejandro Soto | |
| 2022-10-18 | Support skipping tests | Alejandro Soto | |
| 2022-10-18 | Implement register initialization in sim | Alejandro Soto | |
| 2022-10-17 | Improve sim.py output | Alejandro Soto | |
| 2022-10-16 | Implement register dumps | Alejandro Soto | |
| 2022-10-16 | Implement simulation testbenches | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |