| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-10-05 | tb/sim/sdram: lower max cycles | Alejandro Soto | |
| 2022-11-09 | Improve sdram sim test | Alejandro Soto | |
| 2022-11-08 | Fix handling of multi-cycle Avalon waitrequest states in bus master | Alejandro Soto | |
| 2022-11-08 | Add sim: sdram | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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