| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-11-02 | Add new toplevel signals | Alejandro Soto | |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto | |
| 2022-09-18 | Fix public_flat_rw signals | Alejandro Soto | |
| 2022-09-18 | Update testbench | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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