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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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tb
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platform.sv
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Author
2023-10-05
Makefile, tb: add support for cocotb
Alejandro Soto
2023-10-04
rtl/cache: implement debug interface
Alejandro Soto
2023-10-02
tb: implement verilated slaves
Alejandro Soto
2023-10-02
rtl: implement exclusive monitor datapath
Alejandro Soto
2023-10-01
tb: implement quad-core SMP
Alejandro Soto
2023-09-30
platform: implement SMP controller
Alejandro Soto
2023-09-26
rtl/mp: fix design
Alejandro Soto
2023-09-25
rtl/core, tb: replace bus_master with a new top-level module
Alejandro Soto
2023-09-25
tb: implement cache ring
Alejandro Soto
2022-11-17
Bug fixes
JulianCamacho
2022-11-15
Implemente byte-enable signal in stores
Alejandro Soto
2022-11-15
Replace vga_controller with streaming Altera IP
Alejandro Soto
2022-11-14
Implement VGA simulation
Alejandro Soto
2022-11-13
Route cpu_rst_n signal through bus master
Alejandro Soto
2022-11-13
Hardwire PLL reset to ground
Alejandro Soto
2022-11-09
Implement initial state randomization in sim
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-09
Add reset signal to bus master
Alejandro Soto
2022-11-03
Add toplevel wires for VGA DAC
Alejandro Soto
2022-11-02
Add bus master forward signals: irq, cpu_clk
Alejandro Soto
2022-11-02
Add new toplevel signals
Alejandro Soto
2022-09-18
Rename data_rw to data_wr in bus master
Alejandro Soto
2022-09-18
Fix public_flat_rw signals
Alejandro Soto
2022-09-18
Update testbench
Alejandro Soto