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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2022-12-16
Implement hardware virtual memory
Alejandro Soto
2022-12-08
Support gdb interrupts
Alejandro Soto
2022-12-07
Make --no-tty optional in sim
Alejandro Soto
2022-12-07
Make the cycle limit optional
Alejandro Soto
2022-12-07
Implement single-stepping
Alejandro Soto
2022-12-06
Implement gdbstub
Alejandro Soto
2022-11-19
Implement JTAG-UART input
Alejandro Soto
2022-11-17
Implement sim test: descifrador
Alejandro Soto
2022-11-14
Implement VGA simulation
Alejandro Soto
2022-11-10
Implement support for predictable x-values in sim
Alejandro Soto
2022-11-09
Implement initial state randomization in sim
Alejandro Soto
2022-11-07
Improve mult sim
Alejandro Soto
2022-10-31
Show simulator output in sim testbenches
Alejandro Soto
2022-10-25
Implement explicit sim state dump
Alejandro Soto
2022-10-18
Print simulator command line on test failure
Alejandro Soto
2022-10-18
Support skipping tests
Alejandro Soto
2022-10-18
Implement register initialization in sim
Alejandro Soto
2022-10-17
Improve sim.py output
Alejandro Soto
2022-10-16
Implement register dumps
Alejandro Soto
2022-10-16
Implement simulation testbenches
Alejandro Soto