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2022-11-09Update fetch, decode testbenchesAlejandro Soto
2022-11-08Fix handling of multi-cycle Avalon waitrequest states in bus masterAlejandro Soto
2022-11-08Add missing toplevel pin connectionsAlejandro Soto
2022-11-08Improve ALU performanceAlejandro Soto
2022-11-08Register decode output in a new porch stageAlejandro Soto
2022-11-08Rename datapath_decode as ctrl_decodeAlejandro Soto
2022-11-08Refactor decode signals into unified insn_decode structAlejandro Soto
2022-11-07Añade testbench para fetch y decodeJulianCamacho
2022-11-07Adding decode testJulianCamacho
2022-11-07Fix flags hazard in ADC, SBC, RSCAlejandro Soto
2022-11-07Remove false dependencies on control.issue (long combinational)Alejandro Soto
2022-11-07Fix long combinational path between regs and fetchAlejandro Soto
2022-11-07Rework regfile in order to remove negedge triggerAlejandro Soto
2022-11-07Quartus has not support for unique0Alejandro Soto
2022-11-07Implement multiplication controlAlejandro Soto
2022-11-07Split decode mux logic out of decode.svAlejandro Soto
2022-11-06Add PSR control signal setAlejandro Soto
2022-11-06Implement decode for mrs, msrAlejandro Soto
2022-11-06Export PSRs to simulationAlejandro Soto
2022-11-06Implement PSR modes and interrupt masksAlejandro Soto
2022-11-06Clean-up control.svAlejandro Soto
2022-11-06Move CP15 logic out of control.svAlejandro Soto
2022-11-06Move multiplication logic out of control.svAlejandro Soto
2022-11-06Move load-store logic out of control.svAlejandro Soto
2022-11-06Split regfile read select logic out of control.svAlejandro Soto
2022-11-06Move exception logic out of control.svAlejandro Soto
2022-11-06Move flag update logic to writeback.svAlejandro Soto
2022-11-06Split ALU/shifter control logic out of control.svAlejandro Soto
2022-11-06Split branch logic out of control.svAlejandro Soto
2022-11-06Multiplex writeback control signalsAlejandro Soto
2022-11-06Split issue logic out of control.svAlejandro Soto
2022-11-06Add multiplier unitAlejandro Soto
2022-11-03Add toplevel wires for VGA DACAlejandro Soto
2022-11-03platform: add vga controllerJosé Julián
2022-11-02Use PLL output as CPU clockAlejandro Soto
2022-11-02Add bus master forward signals: irq, cpu_clkAlejandro Soto
2022-11-02Move bus/master.sv to bus_master.svAlejandro Soto
2022-11-02Add new toplevel signalsAlejandro Soto
2022-11-01Add CPUID registerAlejandro Soto
2022-11-01Add cp15 primary register mapAlejandro Soto
2022-11-01Add the cp15 subsystemAlejandro Soto
2022-11-01Implement coprocessor instruction decodeAlejandro Soto
2022-11-01Add MUL control cycleAlejandro Soto
2022-11-01Replace decode enable signals with datapath signalsAlejandro Soto
2022-11-01Implement multiplication decodeAlejandro Soto
2022-10-31Display undefined instruction messages in simulationAlejandro Soto
2022-10-31Move mul.sv to rtl/coreAlejandro Soto
2022-10-31Merge branch 'mul'Alejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-27Se agrega algoritmo de BoothJulianCamacho
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