index
:
conspiracion
master
Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
rtl
(
follow
)
Age
Commit message (
Collapse
)
Author
2022-11-07
Implement multiplication control
Alejandro Soto
2022-11-07
Split decode mux logic out of decode.sv
Alejandro Soto
2022-11-06
Add PSR control signal set
Alejandro Soto
2022-11-06
Implement decode for mrs, msr
Alejandro Soto
2022-11-06
Export PSRs to simulation
Alejandro Soto
2022-11-06
Implement PSR modes and interrupt masks
Alejandro Soto
2022-11-06
Clean-up control.sv
Alejandro Soto
2022-11-06
Move CP15 logic out of control.sv
Alejandro Soto
2022-11-06
Move multiplication logic out of control.sv
Alejandro Soto
2022-11-06
Move load-store logic out of control.sv
Alejandro Soto
2022-11-06
Split regfile read select logic out of control.sv
Alejandro Soto
2022-11-06
Move exception logic out of control.sv
Alejandro Soto
2022-11-06
Move flag update logic to writeback.sv
Alejandro Soto
2022-11-06
Split ALU/shifter control logic out of control.sv
Alejandro Soto
2022-11-06
Split branch logic out of control.sv
Alejandro Soto
2022-11-06
Multiplex writeback control signals
Alejandro Soto
2022-11-06
Split issue logic out of control.sv
Alejandro Soto
2022-11-06
Add multiplier unit
Alejandro Soto
2022-11-03
Add toplevel wires for VGA DAC
Alejandro Soto
2022-11-03
platform: add vga controller
José Julián
2022-11-02
Use PLL output as CPU clock
Alejandro Soto
2022-11-02
Add bus master forward signals: irq, cpu_clk
Alejandro Soto
2022-11-02
Move bus/master.sv to bus_master.sv
Alejandro Soto
2022-11-02
Add new toplevel signals
Alejandro Soto
2022-11-01
Add CPUID register
Alejandro Soto
2022-11-01
Add cp15 primary register map
Alejandro Soto
2022-11-01
Add the cp15 subsystem
Alejandro Soto
2022-11-01
Implement coprocessor instruction decode
Alejandro Soto
2022-11-01
Add MUL control cycle
Alejandro Soto
2022-11-01
Replace decode enable signals with datapath signals
Alejandro Soto
2022-11-01
Implement multiplication decode
Alejandro Soto
2022-10-31
Display undefined instruction messages in simulation
Alejandro Soto
2022-10-31
Move mul.sv to rtl/core
Alejandro Soto
2022-10-31
Merge branch 'mul'
Alejandro Soto
2022-10-30
Se agregan test de mul
JulianCamacho
2022-10-27
Se agrega algoritmo de Booth
JulianCamacho
2022-10-25
añade reset
fabian-mv
2022-10-25
mul: refina comentarios y api
fabian-mv
2022-10-25
mul: define api del multiplicador
fabian-mv
2022-10-25
mul: identar con tabs en lugar de espacios
fabian-mv
2022-10-25
mul: pasa a usar tipos definidos en uarch
fabian-mv
2022-10-25
mul: actualiza API de modulo de multiplicación
fabian-mv
2022-10-25
Split mux logic out of control.sv
Alejandro Soto
2022-10-24
Split cycle logic out of control.sv
Alejandro Soto
2022-10-24
Split stall control logic out of control.sv
Alejandro Soto
2022-10-23
Move control cycles enum to public uarch interface
Alejandro Soto
2022-10-23
Pack general control signals as struct datapath_decode
Alejandro Soto
2022-10-23
Move signal `uses_rn` to struct data_decode
Alejandro Soto
2022-10-23
Move branch control signals to struct branch_decode
Alejandro Soto
2022-10-23
Enforce UND exceptions when SBZ is not followed in data-processing instructions
Alejandro Soto
[next]