index
:
conspiracion
master
Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
rtl
(
unfollow
)
Age
Commit message (
Expand
)
Author
2022-12-21
Fix clock/reset timing in single-step, dsp_mul
Alejandro Soto
2022-12-19
Fix spurious high bus_write in page walker
Alejandro Soto
2022-12-18
Implement privileged ldm/stm of user registers
Alejandro Soto
2022-12-18
Implement mode-translated memory accesses
Alejandro Soto
2022-12-18
Fix datapath of shifter carry-out during adc/sbc/rsc
Alejandro Soto
2022-12-16
Fix privilege escalation while in user mode
Alejandro Soto
2022-12-16
Implement mode privilege checks in MMU
Alejandro Soto
2022-12-16
Add interrupt controller to Platform Designer
Alejandro Soto
2022-12-16
Implement swi (system call)
Alejandro Soto
2022-12-16
Implement branch history (simulation only)
Alejandro Soto
2022-12-16
Fix register corruption when interrupting a load-store
Alejandro Soto
2022-12-16
Fix implementation of MMU access faults
Alejandro Soto
2022-12-16
Implement interrupt emulation
Alejandro Soto
2022-12-16
Implement IRQ exceptions
Alejandro Soto
2022-12-16
Implement interrupt controller
Alejandro Soto
2022-12-16
Add cp15 cyclecnt clock source
Alejandro Soto
2022-12-16
Fix sysctrl register dump
Alejandro Soto
2022-12-16
Show main cp15 registers in register dumps
Alejandro Soto
2022-12-16
Implement prefetch aborts
Alejandro Soto
2022-12-16
Implement register writes from gdb
Alejandro Soto
2022-12-16
Implement MMU access checks
Alejandro Soto
2022-12-16
Implement data aborts
Alejandro Soto
2022-12-16
Implement hardware virtual memory
Alejandro Soto
2022-12-10
Expose cp15 signals to core toplevel
Alejandro Soto
2022-12-10
Implement rest of cp15 registers
Alejandro Soto
2022-12-09
Implement CP15 ID register
Alejandro Soto
2022-12-09
Implement cp15 control
Alejandro Soto
2022-12-08
Fix decoding of msr with immediate operand
Alejandro Soto
2022-12-07
Fix register-indirect shifts
Alejandro Soto
2022-12-07
Implement single-stepping
Alejandro Soto
2022-12-06
Implement breakpoints
Alejandro Soto
2022-12-06
Implement gdbstub
Alejandro Soto
2022-11-17
Bug fixes
JulianCamacho
2022-11-16
Fix carry flag bug
Alejandro Soto
2022-11-16
Implement bx lr
Alejandro Soto
2022-11-16
Implement privilege escalation
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Simplify flags datapath
Alejandro Soto
2022-11-16
Finish decode of psr operations
Alejandro Soto
2022-11-16
Fix final_writeback condition bug
Alejandro Soto
2022-11-16
Fix decoding of LDST_MISC group
Alejandro Soto
2022-11-15
Implemente byte-enable signal in stores
Alejandro Soto
2022-11-15
Fix false undefined exception
Alejandro Soto
2022-11-15
Fix shr carry bug
Alejandro Soto
2022-11-15
Implement sub-word memory accesses
Alejandro Soto
2022-11-15
Rewrite duplicate ldst logic as signal ldst_next
Alejandro Soto
2022-11-15
Add untested warning to mul.sv
Alejandro Soto
2022-11-15
Mpve combinational logic out of arm810.sv
Alejandro Soto
2022-11-15
Rename existing MMU components to MMU arbiter
Alejandro Soto
2022-11-15
Replace vga_controller with streaming Altera IP
Alejandro Soto
[next]