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2023-11-17tb: add test: fifoAlejandro Soto
2023-11-16rtl/smp: implement SMP dead/alive handlingAlejandro Soto
2023-10-29rtl/gfx: implement double-buffered scanoutAlejandro Soto
2023-10-28tb: add block test: test_fbAlejandro Soto
2023-10-06tb: implement ring testAlejandro Soto
2023-10-06tb: rename smp_sim to test_smpAlejandro Soto
2023-10-05tb: implement block test: smp_sim resetAlejandro Soto
2023-10-05Makefile, tb: add support for cocotbAlejandro Soto
2023-09-30platform: implement SMP controllerAlejandro Soto
2023-09-25rtl/core, tb: replace bus_master with a new top-level moduleAlejandro Soto
2022-12-21Fix clock/reset timing in single-step, dsp_mulAlejandro Soto
2022-12-07Implement single-steppingAlejandro Soto
2022-12-06Implement breakpointsAlejandro Soto
2022-12-06Implement gdbstubAlejandro Soto
2022-11-17Bug fixesJulianCamacho
2022-11-15Implemente byte-enable signal in storesAlejandro Soto
2022-11-15Replace vga_controller with streaming Altera IPAlejandro Soto
2022-11-14Fix VRAM clockAlejandro Soto
2022-11-13Restore clock connections in Platform DesignerAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-13Route cpu_rst_n signal through bus masterAlejandro Soto
2022-11-13Add reset debounceAlejandro Soto
2022-11-13Hardwire PLL reset to groundAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-11-09Update fetch, decode testbenchesAlejandro Soto
2022-11-08Add missing toplevel pin connectionsAlejandro Soto
2022-11-07Añade testbench para fetch y decodeJulianCamacho
2022-11-07Adding decode testJulianCamacho
2022-11-03Add toplevel wires for VGA DACAlejandro Soto
2022-11-02Use PLL output as CPU clockAlejandro Soto
2022-11-02Add bus master forward signals: irq, cpu_clkAlejandro Soto
2022-11-02Add new toplevel signalsAlejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-02Use @(posedge clk) in register filesAlejandro Soto
2022-09-27Add simple loop execution testbenchAlejandro Soto
2022-09-23Add toplevel module for core testsAlejandro Soto
2022-09-23Rename conspiracion.sv test as hps_sdram_test.svAlejandro Soto
2022-09-19DDR3 is workingAlejandro Soto
2022-09-18Rename data_rw to data_wr in bus masterAlejandro Soto
2022-09-18Update testbenchAlejandro Soto
2022-09-17Update project structure to match Verilator MakefileAlejandro Soto
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