summaryrefslogtreecommitdiff
path: root/rtl/top (follow)
AgeCommit message (Collapse)Author
2022-11-15Replace vga_controller with streaming Altera IPAlejandro Soto
2022-11-14Fix VRAM clockAlejandro Soto
2022-11-13Restore clock connections in Platform DesignerAlejandro Soto
2022-11-13Implement CPU haltAlejandro Soto
2022-11-13Route cpu_rst_n signal through bus masterAlejandro Soto
2022-11-13Add reset debounceAlejandro Soto
2022-11-13Hardwire PLL reset to groundAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-11-09Update fetch, decode testbenchesAlejandro Soto
2022-11-08Add missing toplevel pin connectionsAlejandro Soto
2022-11-07Añade testbench para fetch y decodeJulianCamacho
2022-11-07Adding decode testJulianCamacho
2022-11-03Add toplevel wires for VGA DACAlejandro Soto
2022-11-02Use PLL output as CPU clockAlejandro Soto
2022-11-02Add bus master forward signals: irq, cpu_clkAlejandro Soto
2022-11-02Add new toplevel signalsAlejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-02Use @(posedge clk) in register filesAlejandro Soto
2022-09-27Add simple loop execution testbenchAlejandro Soto
2022-09-23Add toplevel module for core testsAlejandro Soto
2022-09-23Rename conspiracion.sv test as hps_sdram_test.svAlejandro Soto
2022-09-19DDR3 is workingAlejandro Soto
2022-09-18Rename data_rw to data_wr in bus masterAlejandro Soto
2022-09-18Update testbenchAlejandro Soto
2022-09-17Update project structure to match Verilator MakefileAlejandro Soto
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-17 15:39:51 +0000