| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-02 | Add bus master forward signals: irq, cpu_clk | Alejandro Soto |
| 2022-11-02 | Add new toplevel signals | Alejandro Soto |
| 2022-10-30 | Se agregan test de mul | JulianCamacho |
| 2022-10-02 | Use @(posedge clk) in register files | Alejandro Soto |
| 2022-09-27 | Add simple loop execution testbench | Alejandro Soto |
| 2022-09-23 | Add toplevel module for core tests | Alejandro Soto |
| 2022-09-23 | Rename conspiracion.sv test as hps_sdram_test.sv | Alejandro Soto |
| 2022-09-19 | DDR3 is working | Alejandro Soto |
| 2022-09-18 | Rename data_rw to data_wr in bus master | Alejandro Soto |
| 2022-09-18 | Update testbench | Alejandro Soto |
| 2022-09-17 | Update project structure to match Verilator Makefile | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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