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AgeCommit message (Expand)Author
2022-10-24Split stall control logic out of control.svAlejandro Soto
2022-10-23Move control cycles enum to public uarch interfaceAlejandro Soto
2022-10-23Pack general control signals as struct datapath_decodeAlejandro Soto
2022-10-23Move signal `uses_rn` to struct data_decodeAlejandro Soto
2022-10-23Move branch control signals to struct branch_decodeAlejandro Soto
2022-10-23Enforce UND exceptions when SBZ is not followed in data-processing instructionsAlejandro Soto
2022-10-23Fix PC writeback hazardAlejandro Soto
2022-10-23Fix ldm writebackAlejandro Soto
2022-10-23Fix zero-extended (lsr) vs sign-extended (asr) shiftsAlejandro Soto
2022-10-23añade sugerencias y TODOFabián Montero
2022-10-23Fix bad decoding of second-operand immediatesAlejandro Soto
2022-10-20mul: arregla typosfabian-mv
2022-10-19mul: añade base para instrucción MULFabián Montero
2022-10-18Implement branch with linkAlejandro Soto
2022-10-18Support program counter in --dump-regsAlejandro Soto
2022-10-18Implement undefined instruction exceptionsAlejandro Soto
2022-10-17Break sub-100MHz critical path involving wb_alu_flagsAlejandro Soto
2022-10-17Break false dependency on r0 for MOV/MVNAlejandro Soto
2022-10-17Use negative clock edge for register file in Verilator buildsAlejandro Soto
2022-10-17Fix unsafe decode signalsAlejandro Soto
2022-10-17Fix data hazards in nzcv and PC incrementAlejandro Soto
2022-10-16Implement register dumpsAlejandro Soto
2022-10-16Rename cycles as controlAlejandro Soto
2022-10-16Move isa.sv to core/decodeAlejandro Soto
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-15Fix branch target calculationAlejandro Soto
2022-10-15Rework bus architectureAlejandro Soto
2022-10-09Implement most memory transactionsAlejandro Soto
2022-10-09Pipeline flags writeback (breaks combinational data dependencies)Alejandro Soto
2022-10-08Fix writes to PCAlejandro Soto
2022-10-08Implement LDR/STR decodeAlejandro Soto
2022-10-08Rename EXECUTE cycle as ISSUEAlejandro Soto
2022-10-03Fix pipeline hazardsAlejandro Soto
2022-10-02Split decoding of flexible second operand out of data instructionsAlejandro Soto
2022-10-02Make the fetch stage use the bus arbiterAlejandro Soto
2022-10-02Add MMU bus arbiterAlejandro Soto
2022-10-02Use @(posedge clk) in register filesAlejandro Soto
2022-10-02Major shifter-ALU redesignAlejandro Soto
2022-09-27Switch from operand forwarding to next insn stalls (improves Fmax)Alejandro Soto
2022-09-27Fix branching bugsAlejandro Soto
2022-09-27Implement branching in fetch stageAlejandro Soto
2022-09-26Fix MVN (not instead of neg)Alejandro Soto
2022-09-26Fix writeback timingAlejandro Soto
2022-09-26Fix prefetch PC not advancing when buffer is emptyAlejandro Soto
2022-09-26Fix shifter addressing modesAlejandro Soto
2022-09-26Implement ALU shifterAlejandro Soto
2022-09-25Define ALU control signal setAlejandro Soto
2022-09-25Implement shifter decodingAlejandro Soto
2022-09-25Shorten decode_* nets to dec_*Alejandro Soto
2022-09-25Implement flag updatesAlejandro Soto
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