conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-11-15	Implement sub-word memory accesses	Alejandro Soto
2022-11-15	Rewrite duplicate ldst logic as signal ldst_next	Alejandro Soto
2022-11-15	Add untested warning to mul.sv	Alejandro Soto
2022-11-15	Mpve combinational logic out of arm810.sv	Alejandro Soto
2022-11-15	Rename existing MMU components to MMU arbiter	Alejandro Soto
2022-11-13	Fix big Quartus state transition bug	Alejandro Soto
2022-11-13	Convert core state machines to Quartus-inferring RTL	Alejandro Soto
2022-11-13	Implement CPU halt	Alejandro Soto
2022-11-13	Simplify stall conditions to reflect uarch changes	Alejandro Soto
2022-11-10	Fix fetch discard glitches on flush	Alejandro Soto
2022-11-10	Fix reset glitches	Alejandro Soto
2022-11-10	Fix flush-stall relationship in porch	Alejandro Soto
2022-11-09	Implement reset	Alejandro Soto
2022-11-08	Improve ALU performance	Alejandro Soto
2022-11-08	Register decode output in a new porch stage	Alejandro Soto
2022-11-08	Rename datapath_decode as ctrl_decode	Alejandro Soto
2022-11-08	Refactor decode signals into unified insn_decode struct	Alejandro Soto
2022-11-07	Fix flags hazard in ADC, SBC, RSC	Alejandro Soto
2022-11-07	Remove false dependencies on control.issue (long combinational)	Alejandro Soto
2022-11-07	Fix long combinational path between regs and fetch	Alejandro Soto
2022-11-07	Rework regfile in order to remove negedge trigger	Alejandro Soto
2022-11-07	Quartus has not support for unique0	Alejandro Soto
2022-11-07	Implement multiplication control	Alejandro Soto
2022-11-07	Split decode mux logic out of decode.sv	Alejandro Soto
2022-11-06	Add PSR control signal set	Alejandro Soto
2022-11-06	Implement decode for mrs, msr	Alejandro Soto
2022-11-06	Export PSRs to simulation	Alejandro Soto
2022-11-06	Implement PSR modes and interrupt masks	Alejandro Soto
2022-11-06	Clean-up control.sv	Alejandro Soto
2022-11-06	Move CP15 logic out of control.sv	Alejandro Soto
2022-11-06	Move multiplication logic out of control.sv	Alejandro Soto
2022-11-06	Move load-store logic out of control.sv	Alejandro Soto
2022-11-06	Split regfile read select logic out of control.sv	Alejandro Soto
2022-11-06	Move exception logic out of control.sv	Alejandro Soto
2022-11-06	Move flag update logic to writeback.sv	Alejandro Soto
2022-11-06	Split ALU/shifter control logic out of control.sv	Alejandro Soto
2022-11-06	Split branch logic out of control.sv	Alejandro Soto
2022-11-06	Multiplex writeback control signals	Alejandro Soto
2022-11-06	Split issue logic out of control.sv	Alejandro Soto
2022-11-06	Add multiplier unit	Alejandro Soto
2022-11-02	Use PLL output as CPU clock	Alejandro Soto
2022-11-01	Add CPUID register	Alejandro Soto
2022-11-01	Add cp15 primary register map	Alejandro Soto
2022-11-01	Add the cp15 subsystem	Alejandro Soto
2022-11-01	Implement coprocessor instruction decode	Alejandro Soto
2022-11-01	Add MUL control cycle	Alejandro Soto
2022-11-01	Replace decode enable signals with datapath signals	Alejandro Soto
2022-11-01	Implement multiplication decode	Alejandro Soto
2022-10-31	Display undefined instruction messages in simulation	Alejandro Soto
2022-10-31	Move mul.sv to rtl/core	Alejandro Soto