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2022-11-01Add cp15 primary register mapAlejandro Soto
2022-11-01Add the cp15 subsystemAlejandro Soto
2022-11-01Implement coprocessor instruction decodeAlejandro Soto
2022-11-01Add MUL control cycleAlejandro Soto
2022-11-01Replace decode enable signals with datapath signalsAlejandro Soto
2022-11-01Implement multiplication decodeAlejandro Soto
2022-10-31Display undefined instruction messages in simulationAlejandro Soto
2022-10-31Move mul.sv to rtl/coreAlejandro Soto
2022-10-31Merge branch 'mul'Alejandro Soto
2022-10-30Se agregan test de mulJulianCamacho
2022-10-27Se agrega algoritmo de BoothJulianCamacho
2022-10-25añade resetfabian-mv
2022-10-25mul: refina comentarios y apifabian-mv
2022-10-25mul: define api del multiplicadorfabian-mv
2022-10-25mul: identar con tabs en lugar de espaciosfabian-mv
2022-10-25mul: pasa a usar tipos definidos en uarchfabian-mv
2022-10-25mul: actualiza API de modulo de multiplicaciónfabian-mv
2022-10-25Split mux logic out of control.svAlejandro Soto
2022-10-24Split cycle logic out of control.svAlejandro Soto
2022-10-24Split stall control logic out of control.svAlejandro Soto
2022-10-23Move control cycles enum to public uarch interfaceAlejandro Soto
2022-10-23Pack general control signals as struct datapath_decodeAlejandro Soto
2022-10-23Move signal `uses_rn` to struct data_decodeAlejandro Soto
2022-10-23Move branch control signals to struct branch_decodeAlejandro Soto
2022-10-23Enforce UND exceptions when SBZ is not followed in data-processing instructionsAlejandro Soto
2022-10-23Fix PC writeback hazardAlejandro Soto
2022-10-23Fix ldm writebackAlejandro Soto
2022-10-23Fix zero-extended (lsr) vs sign-extended (asr) shiftsAlejandro Soto
2022-10-23añade sugerencias y TODOFabián Montero
2022-10-23Fix bad decoding of second-operand immediatesAlejandro Soto
2022-10-20mul: arregla typosfabian-mv
2022-10-19mul: añade base para instrucción MULFabián Montero
2022-10-18Implement branch with linkAlejandro Soto
2022-10-18Support program counter in --dump-regsAlejandro Soto
2022-10-18Implement undefined instruction exceptionsAlejandro Soto
2022-10-17Break sub-100MHz critical path involving wb_alu_flagsAlejandro Soto
2022-10-17Break false dependency on r0 for MOV/MVNAlejandro Soto
2022-10-17Use negative clock edge for register file in Verilator buildsAlejandro Soto
2022-10-17Fix unsafe decode signalsAlejandro Soto
2022-10-17Fix data hazards in nzcv and PC incrementAlejandro Soto
2022-10-16Implement register dumpsAlejandro Soto
2022-10-16Rename cycles as controlAlejandro Soto
2022-10-16Move isa.sv to core/decodeAlejandro Soto
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-15Fix branch target calculationAlejandro Soto
2022-10-15Rework bus architectureAlejandro Soto
2022-10-09Implement most memory transactionsAlejandro Soto
2022-10-09Pipeline flags writeback (breaks combinational data dependencies)Alejandro Soto
2022-10-08Fix writes to PCAlejandro Soto
2022-10-08Implement LDR/STR decodeAlejandro Soto
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