| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-10-23 | Move control cycles enum to public uarch interface | Alejandro Soto | |
| 2022-10-23 | Pack general control signals as struct datapath_decode | Alejandro Soto | |
| 2022-10-23 | Move signal `uses_rn` to struct data_decode | Alejandro Soto | |
| 2022-10-23 | Move branch control signals to struct branch_decode | Alejandro Soto | |
| 2022-10-17 | Fix unsafe decode signals | Alejandro Soto | |
| 2022-10-09 | Implement most memory transactions | Alejandro Soto | |
| 2022-10-08 | Implement LDR/STR decode | Alejandro Soto | |
| 2022-10-02 | Split decoding of flexible second operand out of data instructions | Alejandro Soto | |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto | |
| The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially. | |||
| 2022-09-25 | Define ALU control signal set | Alejandro Soto | |
| 2022-09-25 | Implement shifter decoding | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-25 | Implement ALU | Alejandro Soto | |
| 2022-09-25 | Implement register file | Alejandro Soto | |
| 2022-09-24 | Implement decode of ALU instructions | Alejandro Soto | |
| 2022-09-23 | Implement initial fetch stage | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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