conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2023-10-05	rtl/perf: implement performance unit	Alejandro Soto
2023-10-02	rtl/core: implement ldrex/strex decode	Alejandro Soto
2023-09-25	rtl/cache: implement wait-for-reply	Alejandro Soto
2023-09-24	rtl/cache: implement	Alejandro Soto
2022-12-16	Implement swi (system call)	Alejandro Soto
2022-12-09	Implement cp15 control	Alejandro Soto
2022-12-07	Implement single-stepping	Alejandro Soto
2022-12-06	Implement breakpoints	Alejandro Soto
2022-11-16	Implement privilege escalation	Alejandro Soto
2022-11-16	Implement psr read/write logic	Alejandro Soto
2022-11-16	Finish decode of psr operations	Alejandro Soto
2022-11-13	Convert core state machines to Quartus-inferring RTL	Alejandro Soto
2022-11-08	Rename datapath_decode as ctrl_decode	Alejandro Soto
2022-11-08	Refactor decode signals into unified insn_decode struct	Alejandro Soto
2022-11-07	Rework regfile in order to remove negedge trigger	Alejandro Soto
2022-11-07	Implement multiplication control	Alejandro Soto
2022-11-06	Add PSR control signal set	Alejandro Soto
2022-11-06	Implement decode for mrs, msr	Alejandro Soto
2022-11-06	Implement PSR modes and interrupt masks	Alejandro Soto
2022-11-06	Add multiplier unit	Alejandro Soto
2022-11-01	Add cp15 primary register map	Alejandro Soto
2022-11-01	Implement coprocessor instruction decode	Alejandro Soto
2022-11-01	Add MUL control cycle	Alejandro Soto
2022-11-01	Replace decode enable signals with datapath signals	Alejandro Soto
2022-11-01	Implement multiplication decode	Alejandro Soto
2022-10-23	Move control cycles enum to public uarch interface	Alejandro Soto
2022-10-23	Pack general control signals as struct datapath_decode	Alejandro Soto
2022-10-23	Move signal `uses_rn` to struct data_decode	Alejandro Soto
2022-10-23	Move branch control signals to struct branch_decode	Alejandro Soto
2022-10-17	Fix unsafe decode signals	Alejandro Soto
2022-10-09	Implement most memory transactions	Alejandro Soto
2022-10-08	Implement LDR/STR decode	Alejandro Soto
2022-10-02	Split decoding of flexible second operand out of data instructions	Alejandro Soto
2022-10-02	Major shifter-ALU redesign	Alejandro Soto
2022-09-25	Define ALU control signal set	Alejandro Soto
2022-09-25	Implement shifter decoding	Alejandro Soto
2022-09-25	Refactor CPSR and uarch.sv	Alejandro Soto
2022-09-25	Implement ALU	Alejandro Soto
2022-09-25	Implement register file	Alejandro Soto
2022-09-24	Implement decode of ALU instructions	Alejandro Soto
2022-09-23	Implement initial fetch stage	Alejandro Soto