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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2024-02-20
rtl: refactor filenames and directory hierarchy
Alejandro Soto
2023-09-25
rtl/core, tb: replace bus_master with a new top-level module
Alejandro Soto
2022-11-10
Fix reset glitches
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-07
Fix long combinational path between regs and fetch
Alejandro Soto
2022-11-07
Rework regfile in order to remove negedge trigger
Alejandro Soto
2022-10-17
Use negative clock edge for register file in Verilator builds
Alejandro Soto
2022-10-16
Implement register dumps
Alejandro Soto
2022-10-09
Pipeline flags writeback (breaks combinational data dependencies)
Alejandro Soto
2022-10-03
Fix pipeline hazards
Alejandro Soto
2022-10-02
Use @(posedge clk) in register files
Alejandro Soto
2022-09-27
Switch from operand forwarding to next insn stalls (improves Fmax)
Alejandro Soto
2022-09-27
Fix branching bugs
Alejandro Soto
2022-09-25
Refactor CPSR and uarch.sv
Alejandro Soto
2022-09-25
Fix Quartus issues
Alejandro Soto
2022-09-25
Implement register file
Alejandro Soto