| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-02-20 | rtl: refactor filenames and directory hierarchy | Alejandro Soto | |
| 2022-11-08 | Register decode output in a new porch stage | Alejandro Soto | |
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto | |
| 2022-10-15 | Fix flags and writeback hazards | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-24 | Implement initial decoder | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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