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AgeCommit message (Collapse)Author
2023-10-02rtl: implement exclusive monitor datapathAlejandro Soto
2022-12-19Fix spurious high bus_write in page walkerAlejandro Soto
2022-12-18Implement mode-translated memory accessesAlejandro Soto
2022-12-16Implement mode privilege checks in MMUAlejandro Soto
2022-12-16Fix implementation of MMU access faultsAlejandro Soto
2022-12-16Implement prefetch abortsAlejandro Soto
2022-12-16Implement MMU access checksAlejandro Soto
2022-12-16Implement data abortsAlejandro Soto
2022-12-16Implement hardware virtual memoryAlejandro Soto
2022-12-10Implement rest of cp15 registersAlejandro Soto
2022-11-15Implemente byte-enable signal in storesAlejandro Soto
2022-11-15Rename existing MMU components to MMU arbiterAlejandro Soto
2022-11-13Convert core state machines to Quartus-inferring RTLAlejandro Soto
2022-11-10Fix fetch discard glitches on flushAlejandro Soto
2022-11-10Fix reset glitchesAlejandro Soto
2022-11-09Implement resetAlejandro Soto
2022-10-15Fix flags and writeback hazardsAlejandro Soto
2022-10-15Rework bus architectureAlejandro Soto
2022-10-02Add MMU bus arbiterAlejandro Soto
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