| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-10-02 | rtl: implement exclusive monitor datapath | Alejandro Soto | |
| 2022-12-18 | Implement mode-translated memory accesses | Alejandro Soto | |
| 2022-12-16 | Implement mode privilege checks in MMU | Alejandro Soto | |
| 2022-12-16 | Implement prefetch aborts | Alejandro Soto | |
| 2022-12-16 | Implement MMU access checks | Alejandro Soto | |
| 2022-12-16 | Implement data aborts | Alejandro Soto | |
| 2022-12-16 | Implement hardware virtual memory | Alejandro Soto | |
| 2022-11-15 | Implemente byte-enable signal in stores | Alejandro Soto | |
| 2022-11-15 | Rename existing MMU components to MMU arbiter | Alejandro Soto | |
| 2022-11-13 | Convert core state machines to Quartus-inferring RTL | Alejandro Soto | |
| 2022-11-10 | Fix fetch discard glitches on flush | Alejandro Soto | |
| 2022-11-10 | Fix reset glitches | Alejandro Soto | |
| 2022-11-09 | Implement reset | Alejandro Soto | |
| 2022-10-15 | Fix flags and writeback hazards | Alejandro Soto | |
| 2022-10-15 | Rework bus architecture | Alejandro Soto | |
| 2022-10-02 | Add MMU bus arbiter | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |