| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-10-17 | Fix data hazards in nzcv and PC increment | Alejandro Soto | |
| 2022-10-15 | Rework bus architecture | Alejandro Soto | |
| 2022-09-27 | Implement branching in fetch stage | Alejandro Soto | |
| 2022-09-26 | Fix prefetch PC not advancing when buffer is empty | Alejandro Soto | |
| 2022-09-25 | Add fetch jump target | Alejandro Soto | |
| 2022-09-25 | Fetch NOP on prefetch flush | Alejandro Soto | |
| 2022-09-23 | Add toplevel module for core tests | Alejandro Soto | |
| 2022-09-23 | Implement initial fetch stage | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |