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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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fetch
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2022-12-16
Implement prefetch aborts
Alejandro Soto
2022-12-16
Implement register writes from gdb
Alejandro Soto
2022-12-07
Implement single-stepping
Alejandro Soto
2022-11-15
Mpve combinational logic out of arm810.sv
Alejandro Soto
2022-11-10
Fix fetch discard glitches on flush
Alejandro Soto
2022-11-10
Fix flush-stall relationship in porch
Alejandro Soto
2022-11-09
Implement reset
Alejandro Soto
2022-11-08
Register decode output in a new porch stage
Alejandro Soto
2022-11-07
Fix long combinational path between regs and fetch
Alejandro Soto
2022-10-17
Fix data hazards in nzcv and PC increment
Alejandro Soto
2022-10-15
Rework bus architecture
Alejandro Soto
2022-09-27
Implement branching in fetch stage
Alejandro Soto
2022-09-26
Fix prefetch PC not advancing when buffer is empty
Alejandro Soto
2022-09-25
Add fetch jump target
Alejandro Soto
2022-09-25
Fetch NOP on prefetch flush
Alejandro Soto
2022-09-23
Add toplevel module for core tests
Alejandro Soto
2022-09-23
Implement initial fetch stage
Alejandro Soto