| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-11-08 | Register decode output in a new porch stage | Alejandro Soto | |
| 2022-11-07 | Fix long combinational path between regs and fetch | Alejandro Soto | |
| 2022-10-17 | Fix data hazards in nzcv and PC increment | Alejandro Soto | |
| 2022-10-15 | Rework bus architecture | Alejandro Soto | |
| 2022-09-27 | Implement branching in fetch stage | Alejandro Soto | |
| 2022-09-25 | Add fetch jump target | Alejandro Soto | |
| 2022-09-23 | Implement initial fetch stage | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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