| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-10-08 | Implement LDR/STR decode | Alejandro Soto | |
| 2022-10-02 | Split decoding of flexible second operand out of data instructions | Alejandro Soto | |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto | |
| The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially. | |||
| 2022-09-27 | Fix branching bugs | Alejandro Soto | |
| 2022-09-26 | Fix shifter addressing modes | Alejandro Soto | |
| 2022-09-25 | Implement shifter decoding | Alejandro Soto | |
| 2022-09-25 | Implement flag updates | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-25 | Fix Quartus issues | Alejandro Soto | |
| 2022-09-25 | Implement ALU opcode decoding | Alejandro Soto | |
| 2022-09-25 | Implement branch handling in decode | Alejandro Soto | |
| 2022-09-25 | Use word/ptr instead of logic[..] | Alejandro Soto | |
| 2022-09-24 | Implement initial decoder | Alejandro Soto | |
| 2022-09-24 | Implement decode of branch instructions | Alejandro Soto | |
| 2022-09-24 | Implement decode of ALU instructions | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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