| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-10-17 | Fix unsafe decode signals | Alejandro Soto |
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto |
| 2022-10-09 | Implement most memory transactions | Alejandro Soto |
| 2022-10-08 | Implement LDR/STR decode | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
| summaryrefslogtreecommitdiff |