| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-10-02 | rtl/core: implement ldrex/strex decode | Alejandro Soto | |
| 2022-12-08 | Fix decoding of msr with immediate operand | Alejandro Soto | |
| 2022-12-06 | Implement breakpoints | Alejandro Soto | |
| 2022-11-16 | Implement bx lr | Alejandro Soto | |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto | |
| 2022-11-16 | Fix decoding of LDST_MISC group | Alejandro Soto | |
| 2022-11-08 | Improve ALU performance | Alejandro Soto | |
| 2022-11-06 | Implement decode for mrs, msr | Alejandro Soto | |
| 2022-11-01 | Implement coprocessor instruction decode | Alejandro Soto | |
| 2022-11-01 | Implement multiplication decode | Alejandro Soto | |
| 2022-10-23 | Enforce UND exceptions when SBZ is not followed in data-processing instructions | Alejandro Soto | |
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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