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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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rtl
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decode
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isa.sv
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Author
2022-12-08
Fix decoding of msr with immediate operand
Alejandro Soto
2022-12-06
Implement breakpoints
Alejandro Soto
2022-11-16
Implement bx lr
Alejandro Soto
2022-11-16
Implement psr read/write logic
Alejandro Soto
2022-11-16
Fix decoding of LDST_MISC group
Alejandro Soto
2022-11-08
Improve ALU performance
Alejandro Soto
2022-11-06
Implement decode for mrs, msr
Alejandro Soto
2022-11-01
Implement coprocessor instruction decode
Alejandro Soto
2022-11-01
Implement multiplication decode
Alejandro Soto
2022-10-23
Enforce UND exceptions when SBZ is not followed in data-processing instructions
Alejandro Soto
2022-10-16
Move isa.sv to core/decode
Alejandro Soto
2022-10-09
Implement most memory transactions
Alejandro Soto
2022-10-08
Implement LDR/STR decode
Alejandro Soto
2022-10-02
Split decoding of flexible second operand out of data instructions
Alejandro Soto
2022-09-25
Implement shifter decoding
Alejandro Soto
2022-09-25
Refactor CPSR and uarch.sv
Alejandro Soto
2022-09-25
Implement ALU
Alejandro Soto
2022-09-25
Implement register file
Alejandro Soto
2022-09-24
Implement decode of ALU instructions
Alejandro Soto
2022-09-24
Add instruction encodings
Alejandro Soto