| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-12-16 | Implement swi (system call) | Alejandro Soto | |
| 2022-12-07 | Implement single-stepping | Alejandro Soto | |
| 2022-12-06 | Implement breakpoints | Alejandro Soto | |
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto | |
| 2022-11-16 | Finish decode of psr operations | Alejandro Soto | |
| 2022-11-16 | Fix decoding of LDST_MISC group | Alejandro Soto | |
| 2022-11-08 | Register decode output in a new porch stage | Alejandro Soto | |
| 2022-11-08 | Rename datapath_decode as ctrl_decode | Alejandro Soto | |
| 2022-11-08 | Refactor decode signals into unified insn_decode struct | Alejandro Soto | |
| 2022-11-07 | Fix flags hazard in ADC, SBC, RSC | Alejandro Soto | |
| 2022-11-07 | Split decode mux logic out of decode.sv | Alejandro Soto | |
| 2022-11-06 | Add PSR control signal set | Alejandro Soto | |
| 2022-11-06 | Implement decode for mrs, msr | Alejandro Soto | |
| 2022-11-01 | Implement coprocessor instruction decode | Alejandro Soto | |
| 2022-11-01 | Replace decode enable signals with datapath signals | Alejandro Soto | |
| 2022-11-01 | Implement multiplication decode | Alejandro Soto | |
| 2022-10-23 | Pack general control signals as struct datapath_decode | Alejandro Soto | |
| 2022-10-23 | Move signal `uses_rn` to struct data_decode | Alejandro Soto | |
| 2022-10-23 | Move branch control signals to struct branch_decode | Alejandro Soto | |
| 2022-10-18 | Implement branch with link | Alejandro Soto | |
| 2022-10-18 | Implement undefined instruction exceptions | Alejandro Soto | |
| 2022-10-17 | Break false dependency on r0 for MOV/MVN | Alejandro Soto | |
| 2022-10-17 | Fix unsafe decode signals | Alejandro Soto | |
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto | |
| 2022-10-15 | Fix flags and writeback hazards | Alejandro Soto | |
| 2022-10-09 | Implement most memory transactions | Alejandro Soto | |
| 2022-10-08 | Implement LDR/STR decode | Alejandro Soto | |
| 2022-10-02 | Split decoding of flexible second operand out of data instructions | Alejandro Soto | |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto | |
| The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially. | |||
| 2022-09-27 | Fix branching bugs | Alejandro Soto | |
| 2022-09-25 | Implement shifter decoding | Alejandro Soto | |
| 2022-09-25 | Implement flag updates | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-25 | Fix Quartus issues | Alejandro Soto | |
| 2022-09-25 | Implement ALU opcode decoding | Alejandro Soto | |
| 2022-09-25 | Implement branch handling in decode | Alejandro Soto | |
| 2022-09-24 | Implement initial decoder | Alejandro Soto | |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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