| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-09-25 | rtl/core, tb: replace bus_master with a new top-level module | Alejandro Soto |
| 2022-11-07 | Fix flags hazard in ADC, SBC, RSC | Alejandro Soto |
| 2022-10-23 | Move signal `uses_rn` to struct data_decode | Alejandro Soto |
| 2022-10-17 | Break false dependency on r0 for MOV/MVN | Alejandro Soto |
| 2022-10-16 | Move isa.sv to core/decode | Alejandro Soto |
| 2022-10-02 | Split decoding of flexible second operand out of data instructions | Alejandro Soto |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto |
| 2022-09-26 | Fix shifter addressing modes | Alejandro Soto |
| 2022-09-25 | Implement shifter decoding | Alejandro Soto |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto |
| 2022-09-25 | Implement ALU opcode decoding | Alejandro Soto |
| 2022-09-25 | Use word/ptr instead of logic[..] | Alejandro Soto |
| 2022-09-24 | Implement decode of ALU instructions | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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