conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2023-11-16	rtl/smp: implement SMP dead/alive handling	Alejandro Soto
2023-10-28	platform: implement support for disabling CPUs	Alejandro Soto
2023-10-02	rtl: implement exclusive monitor datapath	Alejandro Soto
2023-10-01	tb: implement quad-core SMP	Alejandro Soto
2023-09-25	rtl/core, tb: replace bus_master with a new top-level module	Alejandro Soto
2022-11-15	Implemente byte-enable signal in stores	Alejandro Soto
2022-11-13	Convert core state machines to Quartus-inferring RTL	Alejandro Soto
2022-11-13	Route cpu_rst_n signal through bus master	Alejandro Soto
2022-11-10	Fix reset glitches	Alejandro Soto
2022-11-09	Implement reset	Alejandro Soto
2022-11-09	Add reset signal to bus master	Alejandro Soto
2022-11-09	Fix bus protocol errors in bus master	Alejandro Soto
2022-11-08	Fix handling of multi-cycle Avalon waitrequest states in bus master	Alejandro Soto
2022-11-02	Add bus master forward signals: irq, cpu_clk	Alejandro Soto
2022-11-02	Move bus/master.sv to bus_master.sv	Alejandro Soto
2022-10-15	Rework bus architecture	Alejandro Soto
2022-09-18	Rename data_rw to data_wr in bus master	Alejandro Soto
2022-09-18	Fix memory simulation	Alejandro Soto
2022-09-17	Update project structure to match Verilator Makefile	Alejandro Soto
2022-09-04	Add Avalon bus master	Alejandro Soto