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Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.
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2022-11-06
Split issue logic out of control.sv
Alejandro Soto
2022-11-01
Add the cp15 subsystem
Alejandro Soto
2022-11-01
Add MUL control cycle
Alejandro Soto
2022-11-01
Replace decode enable signals with datapath signals
Alejandro Soto
2022-10-31
Display undefined instruction messages in simulation
Alejandro Soto
2022-10-25
Split mux logic out of control.sv
Alejandro Soto
2022-10-24
Split cycle logic out of control.sv
Alejandro Soto
2022-10-24
Split stall control logic out of control.sv
Alejandro Soto
2022-10-23
Move control cycles enum to public uarch interface
Alejandro Soto
2022-10-23
Pack general control signals as struct datapath_decode
Alejandro Soto
2022-10-23
Move signal `uses_rn` to struct data_decode
Alejandro Soto
2022-10-23
Move branch control signals to struct branch_decode
Alejandro Soto
2022-10-23
Fix PC writeback hazard
Alejandro Soto
2022-10-23
Fix ldm writeback
Alejandro Soto
2022-10-18
Implement branch with link
Alejandro Soto
2022-10-18
Support program counter in --dump-regs
Alejandro Soto
2022-10-18
Implement undefined instruction exceptions
Alejandro Soto
2022-10-17
Break sub-100MHz critical path involving wb_alu_flags
Alejandro Soto
2022-10-17
Break false dependency on r0 for MOV/MVN
Alejandro Soto
2022-10-17
Fix data hazards in nzcv and PC increment
Alejandro Soto
2022-10-16
Rename cycles as control
Alejandro Soto
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