| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-11-16 | Implement psr read/write logic | Alejandro Soto |
| 2022-11-16 | Simplify flags datapath | Alejandro Soto |
| 2022-11-13 | Convert core state machines to Quartus-inferring RTL | Alejandro Soto |
| 2022-11-13 | Implement CPU halt | Alejandro Soto |
| 2022-11-13 | Simplify stall conditions to reflect uarch changes | Alejandro Soto |
| 2022-11-09 | Implement reset | Alejandro Soto |
| 2022-11-08 | Refactor decode signals into unified insn_decode struct | Alejandro Soto |
| 2022-11-06 | Add PSR control signal set | Alejandro Soto |
| 2022-11-01 | Add MUL control cycle | Alejandro Soto |
| 2022-10-24 | Split cycle logic out of control.sv | Alejandro Soto |
| 2022-10-24 | Split stall control logic out of control.sv | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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