conspiracion - Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.

Age	Commit message (Expand)	Author
2022-11-06	Clean-up control.sv	Alejandro Soto
2022-11-06	Move CP15 logic out of control.sv	Alejandro Soto
2022-11-06	Move multiplication logic out of control.sv	Alejandro Soto
2022-11-06	Move load-store logic out of control.sv	Alejandro Soto
2022-11-06	Split regfile read select logic out of control.sv	Alejandro Soto
2022-11-06	Move exception logic out of control.sv	Alejandro Soto
2022-11-06	Move flag update logic to writeback.sv	Alejandro Soto
2022-11-06	Split ALU/shifter control logic out of control.sv	Alejandro Soto
2022-11-06	Split branch logic out of control.sv	Alejandro Soto
2022-11-06	Multiplex writeback control signals	Alejandro Soto
2022-11-06	Split issue logic out of control.sv	Alejandro Soto
2022-11-01	Add the cp15 subsystem	Alejandro Soto
2022-11-01	Add MUL control cycle	Alejandro Soto
2022-11-01	Replace decode enable signals with datapath signals	Alejandro Soto
2022-10-31	Display undefined instruction messages in simulation	Alejandro Soto
2022-10-25	Split mux logic out of control.sv	Alejandro Soto
2022-10-24	Split cycle logic out of control.sv	Alejandro Soto
2022-10-24	Split stall control logic out of control.sv	Alejandro Soto
2022-10-23	Move control cycles enum to public uarch interface	Alejandro Soto
2022-10-23	Pack general control signals as struct datapath_decode	Alejandro Soto
2022-10-23	Move signal `uses_rn` to struct data_decode	Alejandro Soto
2022-10-23	Move branch control signals to struct branch_decode	Alejandro Soto
2022-10-23	Fix PC writeback hazard	Alejandro Soto
2022-10-23	Fix ldm writeback	Alejandro Soto
2022-10-18	Implement branch with link	Alejandro Soto
2022-10-18	Support program counter in --dump-regs	Alejandro Soto
2022-10-18	Implement undefined instruction exceptions	Alejandro Soto
2022-10-17	Break sub-100MHz critical path involving wb_alu_flags	Alejandro Soto
2022-10-17	Break false dependency on r0 for MOV/MVN	Alejandro Soto
2022-10-17	Fix data hazards in nzcv and PC increment	Alejandro Soto
2022-10-16	Rename cycles as control	Alejandro Soto
2022-10-15	Fix flags and writeback hazards	Alejandro Soto
2022-10-15	Fix branch target calculation	Alejandro Soto
2022-10-09	Implement most memory transactions	Alejandro Soto
2022-10-08	Implement LDR/STR decode	Alejandro Soto
2022-10-08	Rename EXECUTE cycle as ISSUE	Alejandro Soto
2022-10-03	Fix pipeline hazards	Alejandro Soto
2022-10-02	Split decoding of flexible second operand out of data instructions	Alejandro Soto
2022-10-02	Major shifter-ALU redesign	Alejandro Soto
2022-09-27	Switch from operand forwarding to next insn stalls (improves Fmax)	Alejandro Soto
2022-09-26	Fix writeback timing	Alejandro Soto
2022-09-26	Implement ALU shifter	Alejandro Soto
2022-09-25	Define ALU control signal set	Alejandro Soto
2022-09-25	Implement shifter decoding	Alejandro Soto
2022-09-25	Shorten decode_* nets to dec_*	Alejandro Soto
2022-09-25	Implement flag updates	Alejandro Soto
2022-09-25	Refactor CPSR and uarch.sv	Alejandro Soto
2022-09-25	Fix Quartus issues	Alejandro Soto
2022-09-25	Implement PSR flag handling	Alejandro Soto
2022-09-25	Implement initial cycle control logic	Alejandro Soto