| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-02-20 | rtl: refactor filenames and directory hierarchy | Alejandro Soto | |
| 2022-12-18 | Fix datapath of shifter carry-out during adc/sbc/rsc | Alejandro Soto | |
| 2022-11-16 | Fix carry flag bug | Alejandro Soto | |
| 2022-11-08 | Improve ALU performance | Alejandro Soto | |
| 2022-10-02 | Major shifter-ALU redesign | Alejandro Soto | |
| The shifter unit now works in parallel with the ALU and is no longer part of it. Instructions that use the shifter as input to the ALU will now take an additional cycle, unless the control unit can detect a "trivial shift" situation where the shifter's output will be the same as its input. This change improves Fmax substantially. | |||
| 2022-09-26 | Fix MVN (not instead of neg) | Alejandro Soto | |
| 2022-09-26 | Fix shifter addressing modes | Alejandro Soto | |
| 2022-09-26 | Implement ALU shifter | Alejandro Soto | |
| 2022-09-25 | Define ALU control signal set | Alejandro Soto | |
| 2022-09-25 | Refactor CPSR and uarch.sv | Alejandro Soto | |
| 2022-09-25 | Implement ALU | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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