| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-10-05 | rtl/perf: implement performance unit | Alejandro Soto | |
| 2023-10-04 | añade descripción de registro | Fabian Montero | |
| 2023-10-04 | rtl/cache: increase to 64KiB per core | Alejandro Soto | |
| 2023-10-04 | rtl/cache: implement debug interface | Alejandro Soto | |
| 2023-10-02 | rtl: implement exclusive monitor datapath | Alejandro Soto | |
| 2023-09-29 | platform: add CPUs and caches to qsys | Alejandro Soto | |
| 2023-09-25 | rtl/cache: implement wait-for-reply | Alejandro Soto | |
| 2023-09-24 | rtl/cache: implement | Alejandro Soto | |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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