| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-02-20 | rtl: refactor filenames and directory hierarchy | Alejandro Soto |
| 2023-10-06 | rtl/cache: split mem.sv out of cache_control.sv | Alejandro Soto |
| 2023-10-06 | rtl/cache: split ring.sv out of cache_control.sv | Alejandro Soto |
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index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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