| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-10-06 | rtl/cache: split ring.sv out of cache_control.sv | Alejandro Soto |
| 2023-10-06 | rtl/cache: split token.sv out of cache_control.vs | Alejandro Soto |
| 2023-10-04 | rtl/cache: implement debug interface | Alejandro Soto |
| 2023-10-03 | rtl/cache: implement ll/sc line monitor | Alejandro Soto |
| 2023-10-02 | rtl: implement exclusive monitor datapath | Alejandro Soto |
| 2023-09-29 | platform: add CPUs and caches to qsys | Alejandro Soto |
| 2023-09-25 | rtl/cache: implement wait-for-reply | Alejandro Soto |
| 2023-09-24 | rtl/cache: implement | Alejandro Soto |
 |
index : conspiracion | |
| Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. |
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